linux-kernel - Re: [PATCH v3 13/16] dt-bindings: net: Add DT bindings for DWMAC on NXP S32G/R SoCs

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Message-ID: <ZwzM4tx3zj8+M/Om@lsv051416.swis.nl-cdc01.nxp.com>
Date: Mon, 14 Oct 2024 09:48:50 +0200
From: Jan Petrous <jan.petrous@....nxp.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@...il.com>,
	Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Jose Abreu <joabreu@...opsys.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Vinod Koul <vkoul@...nel.org>,
	Richard Cochran <richardcochran@...il.com>,
	Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Emil Renner Berthing <kernel@...il.dk>,
	Minda Chen <minda.chen@...rfivetech.com>,
	Nicolas Ferre <nicolas.ferre@...rochip.com>,
	Claudiu Beznea <claudiu.beznea@...on.dev>,
	Iyappan Subramanian <iyappan@...amperecomputing.com>,
	Keyur Chudgar <keyur@...amperecomputing.com>,
	Quan Nguyen <quan@...amperecomputing.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Giuseppe Cavallaro <peppe.cavallaro@...com>,
	linux-stm32@...md-mailman.stormreply.com,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	netdev@...r.kernel.org, linux-arm-msm@...r.kernel.org,
	imx@...ts.linux.dev, devicetree@...r.kernel.org,
	NXP S32 Linux Team <s32@....com>
Subject: Re: [PATCH v3 13/16] dt-bindings: net: Add DT bindings for DWMAC on
 NXP S32G/R SoCs

On Mon, Oct 14, 2024 at 08:56:58AM +0200, Krzysztof Kozlowski wrote:
> On 13/10/2024 23:27, Jan Petrous via B4 Relay wrote:
> > From: "Jan Petrous (OSS)" <jan.petrous@....nxp.com>
> > 
> > Add basic description for DWMAC ethernet IP on NXP S32G2xx, S32G3xx
> > and S32R45 automotive series SoCs.
> > 
> > Signed-off-by: Jan Petrous (OSS) <jan.petrous@....nxp.com>
> > ---
> >  .../devicetree/bindings/net/nxp,s32-dwmac.yaml     | 97 ++++++++++++++++++++++
> >  .../devicetree/bindings/net/snps,dwmac.yaml        |  1 +
> >  2 files changed, 98 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> > new file mode 100644
> > index 000000000000..4c65994cbe8b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> > @@ -0,0 +1,97 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright 2021-2024 NXP
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
> > +
> > +maintainers:
> > +  - Jan Petrous (OSS) <jan.petrous@....nxp.com>
> > +
> > +description:
> > +  This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - nxp,s32g2-dwmac
> 
> Where are the other compatibles? Commit msg mentions several devices.

Well, I removed other compatibles thinking we can re-use this only one
also for other SoCs as, on currect stage, we don't need to do any
SoC specific setup.

Is it ok or shall I reinsert them?

> 
> > +
> > +  reg:
> > +    items:
> > +      - description: Main GMAC registers
> > +      - description: GMAC PHY mode control register
> > +
> 
> ...
> 
> > +
> > +        mdio {
> > +          #address-cells = <1>;
> > +          #size-cells = <0>;
> > +          compatible = "snps,dwmac-mdio";
> > +
> > +          phy0: ethernet-phy@0 {
> > +              reg = <0>;
> > +          };
> > +
> 
> Stray blank line.
> 

Ah, missed it. Thanks. Will fix it in v4.

/Jan