linux-kernel - [PATCH v5 2/4] x86/mce: Remove functions that disable error reporting

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Message-ID: <20241014075318.1936-3-TonyWWang-oc@zhaoxin.com>
Date: Mon, 14 Oct 2024 15:53:16 +0800
From: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
To: <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
	<dave.hansen@...ux.intel.com>, <x86@...nel.org>, <hpa@...or.com>,
	<tony.luck@...el.com>, <linux-kernel@...r.kernel.org>,
	<linux-edac@...r.kernel.org>, <qiuxu.zhuo@...el.com>
CC: <CobeChen@...oxin.com>, <TimGuo@...oxin.com>, <LeoLiu-oc@...oxin.com>,
	Lyle Li <LyleLi@...oxin.com>
Subject: [PATCH v5 2/4] x86/mce: Remove functions that disable error reporting

From: Lyle Li <LyleLi@...oxin.com>

Since all major vendors do not disable MCA_CTL after initialization,
remove the functions that disable error reporting.

Signed-off-by: Lyle Li <LyleLi@...oxin.com>
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@...el.com>
---
 arch/x86/kernel/cpu/mce/core.c | 50 ----------------------------------
 1 file changed, 50 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 1b647869c320..f71b33b96b5b 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -2383,53 +2383,6 @@ int __init mcheck_init(void)
  * mce_syscore: PM support
  */
 
-/*
- * Disable machine checks on suspend and shutdown. We can't really handle
- * them later.
- */
-static void mce_disable_error_reporting(void)
-{
-	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
-	int i;
-
-	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
-		struct mce_bank *b = &mce_banks[i];
-
-		if (b->init)
-			wrmsrl(mca_msr_reg(i, MCA_CTL), 0);
-	}
-	return;
-}
-
-static void vendor_disable_error_reporting(void)
-{
-	/*
-	 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
-	 * MSRs are socket-wide. Disabling them for just a single offlined CPU
-	 * is bad, since it will inhibit reporting for all shared resources on
-	 * the socket like the last level cache (LLC), the integrated memory
-	 * controller (iMC), etc.
-	 */
-	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
-	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
-	    boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
-	    boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
-		return;
-
-	mce_disable_error_reporting();
-}
-
-static int mce_syscore_suspend(void)
-{
-	vendor_disable_error_reporting();
-	return 0;
-}
-
-static void mce_syscore_shutdown(void)
-{
-	vendor_disable_error_reporting();
-}
-
 /*
  * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
  * Only one CPU is active at this time, the others get re-added later using
@@ -2443,8 +2396,6 @@ static void mce_syscore_resume(void)
 }
 
 static struct syscore_ops mce_syscore_ops = {
-	.suspend	= mce_syscore_suspend,
-	.shutdown	= mce_syscore_shutdown,
 	.resume		= mce_syscore_resume,
 };
 
@@ -2729,7 +2680,6 @@ static void mce_disable_cpu(void)
 	if (!cpuhp_tasks_frozen)
 		cmci_clear();
 
-	vendor_disable_error_reporting();
 }
 
 static void mce_reenable_cpu(void)
-- 
2.34.1