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Message-ID: <20241014075318.1936-4-TonyWWang-oc@zhaoxin.com>
Date: Mon, 14 Oct 2024 15:53:17 +0800
From: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
To: <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
<dave.hansen@...ux.intel.com>, <x86@...nel.org>, <hpa@...or.com>,
<tony.luck@...el.com>, <linux-kernel@...r.kernel.org>,
<linux-edac@...r.kernel.org>, <qiuxu.zhuo@...el.com>
CC: <CobeChen@...oxin.com>, <TimGuo@...oxin.com>, <LeoLiu-oc@...oxin.com>,
Lyle Li <LyleLi@...oxin.com>
Subject: [PATCH v5 3/4] x86/mce: Add zhaoxin.c to support Zhaoxin MCA
From: Lyle Li <LyleLi@...oxin.com>
For the sake of code standardization, add zhaoxin.c to
override the Zhaoxin MCA code.
Signed-off-by: Lyle Li <LyleLi@...oxin.com>
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@...el.com>
---
arch/x86/Kconfig | 8 ++++
arch/x86/kernel/cpu/mce/Makefile | 1 +
arch/x86/kernel/cpu/mce/core.c | 57 --------------------------
arch/x86/kernel/cpu/mce/internal.h | 7 ++++
arch/x86/kernel/cpu/mce/zhaoxin.c | 64 ++++++++++++++++++++++++++++++
5 files changed, 80 insertions(+), 57 deletions(-)
create mode 100644 arch/x86/kernel/cpu/mce/zhaoxin.c
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1ea18662942c..a7993835f460 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1183,6 +1183,14 @@ config X86_MCE_INTEL
Additional support for intel specific MCE features such as
the thermal monitor.
+config X86_MCE_ZHAOXIN
+ def_bool y
+ prompt "Zhaoxin MCE features"
+ depends on X86_MCE_INTEL
+ help
+ Additional support for Zhaoxin specific MCE features such as
+ the corrected machine check interrupt.
+
config X86_MCE_AMD
def_bool y
prompt "AMD MCE features"
diff --git a/arch/x86/kernel/cpu/mce/Makefile b/arch/x86/kernel/cpu/mce/Makefile
index 015856abdbb1..7b52c8f2f08e 100644
--- a/arch/x86/kernel/cpu/mce/Makefile
+++ b/arch/x86/kernel/cpu/mce/Makefile
@@ -4,6 +4,7 @@ obj-y = core.o severity.o genpool.o
obj-$(CONFIG_X86_ANCIENT_MCE) += winchip.o p5.o
obj-$(CONFIG_X86_MCE_INTEL) += intel.o
obj-$(CONFIG_X86_MCE_AMD) += amd.o
+obj-$(CONFIG_X86_MCE_ZHAOXIN) += zhaoxin.o
obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o
mce-inject-y := inject.o
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index f71b33b96b5b..a1684b73b349 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1970,17 +1970,6 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
mce_flags.skx_repmov_quirk = 1;
}
- if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
- /*
- * All newer Zhaoxin CPUs support MCE broadcasting. Enable
- * synchronization with a one second timeout.
- */
- if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
- if (cfg->monarch_timeout < 0)
- cfg->monarch_timeout = USEC_PER_SEC;
- }
- }
-
if (cfg->monarch_timeout < 0)
cfg->monarch_timeout = 0;
if (cfg->bootlog != 0)
@@ -2023,49 +2012,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
}
}
-static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
-{
- struct mca_config *cfg = &mca_cfg;
-
- /*
- * All newer Centaur CPUs support MCE broadcasting. Enable
- * synchronization with a one second timeout.
- */
- if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
- c->x86 > 6) {
- if (cfg->monarch_timeout < 0)
- cfg->monarch_timeout = USEC_PER_SEC;
- }
-}
-
-static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
-{
- struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
-
- /*
- * These CPUs have MCA bank 8 which reports only one error type called
- * SVAD (System View Address Decoder). The reporting of that error is
- * controlled by IA32_MC8.CTL.0.
- *
- * If enabled, prefetching on these CPUs will cause SVAD MCE when
- * virtual machines start and result in a system panic. Always disable
- * bank 8 SVAD error by default.
- */
- if ((c->x86 == 7 && c->x86_model == 0x1b) ||
- (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
- if (this_cpu_read(mce_num_banks) > 8)
- mce_banks[8].ctl = 0;
- }
-
- intel_init_cmci();
- intel_init_lmce();
-}
-
-static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
-{
- intel_clear_lmce();
-}
-
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
{
switch (c->x86_vendor) {
@@ -2083,9 +2029,6 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
break;
case X86_VENDOR_CENTAUR:
- mce_centaur_feature_init(c);
- break;
-
case X86_VENDOR_ZHAOXIN:
mce_zhaoxin_feature_init(c);
break;
diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h
index 43c7f3b71df5..fb9d8b5b3b75 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -336,4 +336,11 @@ static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
}
extern void (*mc_poll_banks)(void);
+#ifdef CONFIG_X86_MCE_ZHAOXIN
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c);
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c);
+#else
+static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { }
+static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { }
+#endif
#endif /* __X86_MCE_INTERNAL_H__ */
diff --git a/arch/x86/kernel/cpu/mce/zhaoxin.c b/arch/x86/kernel/cpu/mce/zhaoxin.c
new file mode 100644
index 000000000000..6fdef2d24f31
--- /dev/null
+++ b/arch/x86/kernel/cpu/mce/zhaoxin.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Zhaoxin specific MCE features
+ * Author: Lyle Li
+ */
+#include <asm/msr.h>
+#include "internal.h"
+
+static void mce_zhaoxin_apply_mce_broadcast(struct cpuinfo_x86 *c)
+{
+ struct mca_config *cfg = &mca_cfg;
+
+ /* Older CPUs do not do MCE broadcast: */
+ if (c->x86 < 6)
+ return;
+
+ /* All newer ones do: */
+ if (c->x86 > 6)
+ goto mce_broadcast;
+
+ /* Family 6 is mixed: */
+ if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+ if (c->x86_model == 0xf && c->x86_stepping >= 0xe)
+ goto mce_broadcast;
+ } else if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+ if (c->x86_model == 0x19 || c->x86_model == 0x1f)
+ goto mce_broadcast;
+ }
+
+ return;
+
+mce_broadcast:
+ if (cfg->monarch_timeout <= 0)
+ cfg->monarch_timeout = USEC_PER_SEC;
+}
+
+void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
+{
+ struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+ /*
+ * These CPUs have MCA bank 8 which reports only one error type called
+ * SVAD (System View Address Decoder). The reporting of that error is
+ * controlled by IA32_MC8.CTL.0.
+ *
+ * If enabled, prefetching on these CPUs will cause SVAD MCE when
+ * virtual machines start and result in a system panic. Always disable
+ * bank 8 SVAD error by default.
+ */
+ if ((c->x86 == 7 && c->x86_model == 0x1b) ||
+ (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+ if (this_cpu_read(mce_num_banks) > 8)
+ mce_banks[8].ctl = 0;
+ }
+
+ mce_zhaoxin_apply_mce_broadcast(c);
+ intel_init_cmci();
+ intel_init_lmce();
+}
+
+void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+ intel_clear_lmce();
+}
--
2.34.1
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