linux-kernel - Re: [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size

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Message-ID: <78a1c5c8-53c8-4144-b311-c34b155ca27c@kernel.org>
Date: Tue, 15 Oct 2024 15:33:00 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jyothi Kumar Seerapu <quic_jseerapu@...cinc.com>,
 Vinod Koul <vkoul@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>, Andi Shyti <andi.shyti@...nel.org>,
 Sumit Semwal <sumit.semwal@...aro.org>,
 Christian König <christian.koenig@....com>
Cc: cros-qcom-dts-watchers@...omium.org, linux-arm-msm@...r.kernel.org,
 dmaengine@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
 linux-media@...r.kernel.org, dri-devel@...ts.freedesktop.org,
 linaro-mm-sig@...ts.linaro.org, quic_msavaliy@...cinc.com,
 quic_vtanuku@...cinc.com
Subject: Re: [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring
 channel TRE size

On 15/10/2024 14:07, Jyothi Kumar Seerapu wrote:
> When high performance with multiple i2c messages in a single transfer
> is required, employ Block Event Interrupt (BEI) to trigger interrupts
> after specific messages transfer and the last message transfer,
> thereby reducing interrupts.
> For each i2c message transfer, a series of Transfer Request Elements(TREs)
> must be programmed, including config tre for frequency configuration,
> go tre for holding i2c address and dma tre for holding dma buffer address,
> length as per the hardware programming guide. For transfer using BEI,
> multiple I2C messages may necessitate the preparation of config, go,
> and tx DMA TREs. However, a channel TRE size of 64 is often insufficient,
> potentially leading to failures due to inadequate memory space.
> 
> Adjust the channel TRE size through the device tree.
> The default size is 64, but clients can modify this value based on
> their heigher channel TRE size requirements.
> 
> Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 132 +++++++++++++--------------
>  1 file changed, 66 insertions(+), 66 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 3d8410683402..c7c0e15ff9d3 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1064,7 +1064,7 @@
>  		};
>  
>  		gpi_dma0: dma-controller@...000 {
> -			#dma-cells = <3>;
> +			#dma-cells = <4>;
>  			compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
>  			reg = <0 0x00900000 0 0x60000>;
>  			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> @@ -1114,8 +1114,8 @@
>  							"qup-memory";
>  				power-domains = <&rpmhpd SC7280_CX>;
>  				required-opps = <&rpmhpd_opp_low_svs>;
> -				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> -				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> +				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C 64>,
> +				       <&gpi_dma0 1 0 QCOM_GPI_I2C 64>;

So everywhere is 64, thus this is fixed. Deduce it from the compatible

Best regards,
Krzysztof