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Message-ID: <4963051.31r3eYUQgx@steina-w>
Date: Tue, 15 Oct 2024 11:18:53 +0200
From: Alexander Stein <alexander.stein@...tq-group.com>
To: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, abelvesa@...nel.org, peng.fan@....com, mturquette@...libre.com, sboyd@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de, festevam@...il.com, Richard Zhu <hongxing.zhu@....com>
Cc: hongxing.zhu@....com, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org, imx@...ts.linux.dev, kernel@...gutronix.de
Subject: Re: [PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block
Hi Richard,
Am Dienstag, 15. Oktober 2024, 09:34:04 CEST schrieb Richard Zhu:
> CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
> enable/disable.
>
> Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF clock
> out gate.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> Reviewed-by: Frank Li <Frank.Li@....com>
> Reviewed-by: Peng Fan <peng.fan@....com>
> ---
> drivers/clk/imx/clk-imx95-blk-ctl.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
> index 19a62da74be4..25974947ad0c 100644
> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> @@ -277,6 +277,25 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
> .clk_reg_offset = 0,
> };
>
> +static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
> + [0] = {
> + .name = "hsio_blk_ctl_clk",
> + .parent_names = (const char *[]){ "hsio_pll", },
> + .num_parents = 1,
> + .reg = 0,
According to RM the register LFAST_IO_REG has offset 0xc0. How does the DT node look like?
If this is the HSIO block control I would have expected this to control the whole block.
Best regards,
Alexander
> + .bit_idx = 6,
> + .bit_width = 1,
> + .type = CLK_GATE,
> + .flags = CLK_SET_RATE_PARENT,
> + }
> +};
> +
> +static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
> + .num_clks = 1,
> + .clk_dev_data = hsio_blk_ctl_clk_dev_data,
> + .clk_reg_offset = 0,
> +};
> +
> static int imx95_bc_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -447,6 +466,7 @@ static const struct of_device_id imx95_bc_of_match[] = {
> { .compatible = "nxp,imx95-display-master-csr", },
> { .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
> { .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
> + { .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
> { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
> { .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
> { /* Sentinel */ },
>
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