linux-kernel - Re: [PATCH 12/15] cxl/pci: Add error handler for CXL PCIe port RAS errors

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Message-ID: <20241017145702.00006e58@Huawei.com>
Date: Thu, 17 Oct 2024 14:57:02 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Terry Bowman <terry.bowman@....com>
CC: <ming4.li@...el.com>, <linux-cxl@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
	<dave@...olabs.net>, <dave.jiang@...el.com>, <alison.schofield@...el.com>,
	<vishal.l.verma@...el.com>, <dan.j.williams@...el.com>,
	<bhelgaas@...gle.com>, <mahesh@...ux.ibm.com>, <oohall@...il.com>,
	<Benjamin.Cheatham@....com>, <rrichter@....com>, <nathan.fontenot@....com>,
	<smita.koralahallichannabasappa@....com>
Subject: Re: [PATCH 12/15] cxl/pci: Add error handler for CXL PCIe port RAS
 errors

On Tue, 8 Oct 2024 17:16:54 -0500
Terry Bowman <terry.bowman@....com> wrote:

> The CXL drivers do not contain error handlers for CXL PCIe port
> device protocol errors. These are needed in order to handle and log
> RAS protocol errors.
> 
> Add CXL PCIe port protocol error handlers to the CXL driver.
> 
> Provide access to RAS registers for the specific CXL PCIe port types:
> root port, upstream switch port, and downstream switch port.
> 
> Also, register and unregister the CXL PCIe port error handlers with
> the AER service driver using register_cxl_port_err_hndlrs() and
> unregister_cxl_port_err_hndlrs(). Invoke the registration from
> cxl_pci_driver_init() and the unregistration from cxl_pci_driver_exit().
> 
> [1] CXL3.1 - 12.2.2 CXL Root Ports, Downstream Switch Ports, and
>              Upstream Switch Ports
> 
> Signed-off-by: Terry Bowman <terry.bowman@....com>
A few comments inline.

Jonathan

> ---
>  drivers/cxl/core/pci.c | 83 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/cxl/cxl.h      |  5 +++
>  drivers/cxl/pci.c      |  8 ++++
>  3 files changed, 96 insertions(+)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index c3c82c051d73..7e3770f7a955 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -815,6 +815,89 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
>  	}
>  }
>  
> +static int match_uport(struct device *dev, const void *data)
> +{
> +	struct device *uport_dev = (struct device *)data;
> +	struct cxl_port *port;
> +
> +	if (!is_cxl_port(dev))
> +		return 0;
> +
> +	port = to_cxl_port(dev);
> +
> +	return port->uport_dev == uport_dev;
> +}
> +
> +static void __iomem *cxl_pci_port_ras(struct pci_dev *pdev)
> +{
> +	void __iomem *ras_base;
> +	struct cxl_port *port;
> +
> +	if (!pdev)
> +		return NULL;
Why would this happen?  Seems an odd check to have so maybe a comment.

> +
> +	if ((pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) ||
> +	    (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)) {
> +		struct cxl_dport *dport;
> +
> +		port = find_cxl_port(&pdev->dev, &dport);
Can in theory fail.
> +		ras_base = dport ? dport->regs.ras : NULL;
> +		put_device(&port->dev);
If it fails this is a null pointer dereference.

> +		return ras_base;
> +	} else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_UPSTREAM) {
> +		struct device *port_dev __free(put_device);

Should be combined with the next line. We want it to be hard for anyone
to put code in between!

> +
> +		port_dev = bus_find_device(&cxl_bus_type, NULL, &pdev->dev, match_uport);
> +		if (!port_dev)
> +			return NULL;
> +
> +		port = to_cxl_port(port_dev);
> +		if (!port)
> +			return NULL;
> +
> +		ras_base = port ? port->uport_regs.ras : NULL;

Given check above, port exists. Remove one of the two
checks.

> +		return ras_base;
> +	}
> +
> +	return NULL;
> +}