linux-kernel - Re: [PATCH] riscv, bpf: Make BPF

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Message-ID: <87iktq7ojc.fsf@all.your.base.are.belong.to.us>
Date: Thu, 17 Oct 2024 17:11:03 +0200
From: Björn Töpel <bjorn@...nel.org>
To: Puranjay Mohan <puranjay@...nel.org>, Andrea Parri
 <parri.andrea@...il.com>, ast@...nel.org, daniel@...earbox.net,
 andrii@...nel.org, martin.lau@...ux.dev, eddyz87@...il.com,
 song@...nel.org, yonghong.song@...ux.dev, john.fastabend@...il.com,
 kpsingh@...nel.org, sdf@...ichev.me, haoluo@...gle.com, jolsa@...nel.org,
 pulehui@...wei.com, paul.walmsley@...ive.com, palmer@...belt.com,
 aou@...s.berkeley.edu, paulmck@...nel.org, puranjay12@...il.com
Cc: bpf@...r.kernel.org, linux-riscv@...ts.infradead.org,
 linux-kernel@...r.kernel.org, Andrea Parri <parri.andrea@...il.com>
Subject: Re: [PATCH] riscv, bpf: Make BPF_CMPXCHG fully ordered

Thanks, Andrea!

Puranjay Mohan <puranjay@...nel.org> writes:

> Andrea Parri <parri.andrea@...il.com> writes:
>
>> According to the prototype formal BPF memory consistency model
>> discussed e.g. in [1] and following the ordering properties of
>> the C/in-kernel macro atomic_cmpxchg(), a BPF atomic operation
>> with the BPF_CMPXCHG modifier is fully ordered.  However, the
>> current RISC-V JIT lowerings fail to meet such memory ordering
>> property.  This is illustrated by the following litmus test:
>>
>> BPF BPF__MP+success_cmpxchg+fence
>> {
>>  0:r1=x; 0:r3=y; 0:r5=1;
>>  1:r2=y; 1:r4=f; 1:r7=x;
>> }
>>  P0                               | P1                                         ;
>>  *(u64 *)(r1 + 0) = 1             | r1 = *(u64 *)(r2 + 0)                      ;
>>  r2 = cmpxchg_64 (r3 + 0, r4, r5) | r3 = atomic_fetch_add((u64 *)(r4 + 0), r5) ;
>>                                   | r6 = *(u64 *)(r7 + 0)                      ;
>> exists (1:r1=1 /\ 1:r6=0)
>>
>> whose "exists" clause is not satisfiable according to the BPF
>> memory model.  Using the current RISC-V JIT lowerings, the test
>> can be mapped to the following RISC-V litmus test:
>>
>> RISCV RISCV__MP+success_cmpxchg+fence
>> {
>>  0:x1=x; 0:x3=y; 0:x5=1;
>>  1:x2=y; 1:x4=f; 1:x7=x;
>> }
>>  P0                 | P1                          ;
>>  sd x5, 0(x1)       | ld x1, 0(x2)                ;
>>  L00:               | amoadd.d.aqrl x3, x5, 0(x4) ;
>>  lr.d x2, 0(x3)     | ld x6, 0(x7)                ;
>>  bne x2, x4, L01    |                             ;
>>  sc.d x6, x5, 0(x3) |                             ;
>>  bne x6, x4, L00    |                             ;
>>  fence rw, rw       |                             ;
>>  L01:               |                             ;
>> exists (1:x1=1 /\ 1:x6=0)
>>
>> where the two stores in P0 can be reordered.  Update the RISC-V
>> JIT lowerings/implementation of BPF_CMPXCHG to emit an SC with
>> RELEASE ("rl") annotation in order to meet the expected memory
>> ordering guarantees.  The resulting RISC-V JIT lowerings of
>> BPF_CMPXCHG match the RISC-V lowerings of the C atomic_cmpxchg().
>
> Thanks for fixing this, I fixed all others in:
>
> 20a759df3bba ("riscv, bpf: make some atomic operations fully ordered")
>
>> Fixes: dd642ccb45ec ("riscv, bpf: Implement more atomic operations for RV64")
>> Signed-off-by: Andrea Parri <parri.andrea@...il.com>
>
> Reviewed-by: Puranjay Mohan <puranjay@...nel.org>

Acked-by: Björn Töpel <bjorn@...nel.org>