linux-kernel - Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter

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Message-ID: <1360191c-de5f-49eb-8085-afebcb0a1c97@nxp.com>
Date: Thu, 17 Oct 2024 17:53:55 +0800
From: Liu Ying <victor.liu@....com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
 Biju Das <biju.das.jz@...renesas.com>
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Subject: Re: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter

On 10/14/2024, Dmitry Baryshkov wrote:
[...]

>>>> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
>>>> +				      struct drm_bridge_state *bridge_state,
>>>> +				      struct drm_crtc_state *crtc_state,
>>>> +				      struct drm_connector_state *conn_state) {
>>>> +	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
>>>
>>> Use drm_atomic_helper_connector_hdmi_check().
>>>
>>> Implement .hdmi_tmds_char_rate_valid(). Also, I think, single and dual link LVDS have different max
>>> clock rates. Please correct me if I'm wrong.
>>
>> I guess this rate will be same for both links in dual lvds mode.
>> For single link, it supports only link0.
>> We cannot operate link1 its Own.
>>
>> From ITE point the max rate is rate corresponding to 1080p(148-150MHz)
>>
>> single and dual link LVDS have different max clock rates, but that constraint is
>> in SoC side?? ITE HW manual does not mention about this.
> 
> Huh? I checked the datasheet, version 0.8.
> It specifies LVDS clock rate (not the mode clock) up to 150 MHz and HDMI

The datasheet says "Features(LVDS RX) * Support input clock rate up to
150MHz".  The 150MHz is the mode clock rate which kind of matches the
words "Features(Combined) * Support up to Full-HD/1080P and UXGA(1600x
1200) display format".  LVDS serial clock rate is either x7 or x3.5
the mode clock rate, depending on single link or dual link.

> rate up to 225 MHz. Please check both constraints.

Will check both constraints.

[...]

>>>> +	it->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
>>>
>>>   | DRM_BRIDGE_OP_HDMI
>>>
>>> BTW: No HPD IRQ support?
>>
>> Renesas SMARC RZ/G3E this signal is internal. No dedicted IRQ line 
>> Populated for this signal. I don't know about NXP and any other platforms
>> has HPD wired to test the HPD IRQ support.
>>
>> Maybe go with poll method now and add hot plug support,
>> when we have platform with HPD to test.
> 
> I'm fine with this. According to the datasheet it doesn't seem to have
> the IRQ pin at all. It's just surprising to me. It's be nice to mention
> that HW doesn't support HPD IRQ either before setting it->bridge.ops or
> in the commit message.

Will mention this before setting it->bridge.ops.

-- 
Regards,
Liu Ying