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Message-ID: <8b022694-ed39-5216-67ed-f532ecb576df@linux.intel.com>
Date: Thu, 17 Oct 2024 13:30:00 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>
cc: linux-pci@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Rob Herring <robh@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
"Maciej W. Rozycki" <macro@...am.me.uk>, Lukas Wunner <lukas@...ner.de>,
Alexandru Gagniuc <mr.nuke.me@...il.com>,
Krishna chaitanya chundru <quic_krichai@...cinc.com>,
Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>,
"Rafael J. Wysocki" <rafael@...nel.org>, linux-pm@...r.kernel.org,
Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>,
Jonathan Corbet <corbet@....net>, linux-doc@...r.kernel.org,
LKML <linux-kernel@...r.kernel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Amit Kucheria <amitk@...nel.org>, Zhang Rui <rui.zhang@...el.com>,
Christophe JAILLET <christophe.jaillet@...adoo.fr>
Subject: Re: [PATCH v8 1/8] PCI: Protect Link Control 2 Register with RMW
locking
On Thu, 17 Oct 2024, Jonathan Cameron wrote:
> On Wed, 9 Oct 2024 12:52:16 +0300
> Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com> wrote:
>
> > PCIe Bandwidth Controller performs RMW accesses the Link Control 2
> > Register which can occur concurrently to other sources of Link Control
> > 2 Register writes. Therefore, add Link Control 2 Register among the PCI
> > Express Capability Registers that need RMW locking.
> >
> > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
> > Reviewed-by: Lukas Wunner <lukas@...ner.de>
> Totally trivial comment inline.
>
> LGTM
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
>
> > ---
> > Documentation/PCI/pciebus-howto.rst | 14 +++++++++-----
> > include/linux/pci.h | 1 +
> > 2 files changed, 10 insertions(+), 5 deletions(-)
> >
> > diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst
> > index f344452651e1..375d9ce171f6 100644
> > --- a/Documentation/PCI/pciebus-howto.rst
> > +++ b/Documentation/PCI/pciebus-howto.rst
> > @@ -217,8 +217,12 @@ capability structure except the PCI Express capability structure,
> > that is shared between many drivers including the service drivers.
> > RMW Capability accessors (pcie_capability_clear_and_set_word(),
> > pcie_capability_set_word(), and pcie_capability_clear_word()) protect
> > -a selected set of PCI Express Capability Registers (Link Control
> > -Register and Root Control Register). Any change to those registers
> > -should be performed using RMW accessors to avoid problems due to
> > -concurrent updates. For the up-to-date list of protected registers,
> > -see pcie_capability_clear_and_set_word().
> > +a selected set of PCI Express Capability Registers:
> > +
> > +* Link Control Register
> > +* Root Control Register
> > +* Link Control 2 Register
> > +
> > +Any change to those registers should be performed using RMW accessors to
> > +avoid problems due to concurrent updates. For the up-to-date list of
> > +protected registers, see pcie_capability_clear_and_set_word().
>
> If I were super fussy I'd ask for a precursor patch doing the reformat.
>
> Meh - up to Bjorn, but for me this is small enough to not be worth
> the effort.
Hi Jonathan,
Thanks. Since you brought it up, I've no problem in splitting the
reformatting into own patch, it won't take more than a minute
anyway to do that change.
--
i.
> > diff --git a/include/linux/pci.h b/include/linux/pci.h
> > index 573b4c4c2be6..be5ed534c39c 100644
> > --- a/include/linux/pci.h
> > +++ b/include/linux/pci.h
> > @@ -1274,6 +1274,7 @@ static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
> > {
> > switch (pos) {
> > case PCI_EXP_LNKCTL:
> > + case PCI_EXP_LNKCTL2:
> > case PCI_EXP_RTCTL:
> > return pcie_capability_clear_and_set_word_locked(dev, pos,
> > clear, set);
>
>
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