linux-kernel - Re: [PATCH] arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1 frequency to 506.8 MHz

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <7094f3c17319ccb4676e7b539fc4bb52bea674e6.camel@phytec.de>
Date: Fri, 18 Oct 2024 07:31:47 +0000
From: Yannic Moog <Y.Moog@...tec.de>
To: "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "marex@...x.de" <marex@...x.de>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"kernel@...gutronix.de" <kernel@...gutronix.de>, "festevam@...il.com"
	<festevam@...il.com>, "isaac.scott@...asonboard.com"
	<isaac.scott@...asonboard.com>, "kernel@...electronics.com"
	<kernel@...electronics.com>, "robh@...nel.org" <robh@...nel.org>,
	"krzk+dt@...nel.org" <krzk+dt@...nel.org>, "victor.liu@....com"
	<victor.liu@....com>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
	"imx@...ts.linux.dev" <imx@...ts.linux.dev>, "shawnguo@...nel.org"
	<shawnguo@...nel.org>, "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH] arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1
 frequency to 506.8 MHz

On Thu, 2024-10-17 at 05:11 +0200, Marek Vasut wrote:
> The LVDS panel on this device uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1
> to 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout engine can
> reach accurate pixel clock of exactly 72.4 MHz.
> 
> Without this patch, the Video PLL1 frequency is the default set in imx8mp.dtsi
> which is 1039.5 MHz, which divides down to inaccurate pixel clock of 74.25 MHz
> which works for this particular panel by sheer chance.
> 
> Stop taking that chance and set correct accurate pixel clock frequency instead.
> 
> Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support")
> Reported-by: Isaac Scott <isaac.scott@...asonboard.com>
> Signed-off-by: Marek Vasut <marex@...x.de>

Reviewed-by: Yannic Moog <y.moog@...tec.de>
Tested-by: Yannic Moog <y.moog@...tec.de>

> ---
> Cc: Conor Dooley <conor+dt@...nel.org>
> Cc: Fabio Estevam <festevam@...il.com>
> Cc: Isaac Scott <isaac.scott@...asonboard.com>
> Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>
> Cc: Liu Ying <victor.liu@....com>
> Cc: Pengutronix Kernel Team <kernel@...gutronix.de>
> Cc: Rob Herring <robh@...nel.org>
> Cc: Sascha Hauer <s.hauer@...gutronix.de>
> Cc: Shawn Guo <shawnguo@...nel.org>
> Cc: Yannic Moog <y.moog@...tec.de>
> Cc: devicetree@...r.kernel.org
> Cc: imx@...ts.linux.dev
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> ---
> Note: I do not have the board, but Isaac reported they tested it successfully.
>       TB would be nice.
> ---
>  .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts     | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> index 50debe821c421..9c102acb8052c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> @@ -218,6 +218,18 @@ ldb_lvds_ch1: endpoint {
>  	};
>  };
>  
> +&media_blk_ctrl {
> +	/*
> +	 * The LVDS panel on this device uses 72.4 MHz pixel clock,
> +	 * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB
> +	 * serializer and LCDIFv3 scanout engine can reach accurate
> +	 * pixel clock of exactly 72.4 MHz.
> +	 */
> +	assigned-clock-rates = <500000000>, <200000000>,
> +			       <0>, <0>, <500000000>,
> +			       <506800000>;
> +};
> +
>  &snvs_pwrkey {
>  	status = "okay";
>  };