linux-kernel - Re: [PATCH] arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1 frequency to 506.8 MHz

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Message-ID: <ZxcafhdxyIwI0Sq2@dragon>
Date: Tue, 22 Oct 2024 11:22:38 +0800
From: Shawn Guo <shawnguo2@...h.net>
To: Marek Vasut <marex@...x.de>
Cc: linux-arm-kernel@...ts.infradead.org, kernel@...electronics.com,
	Isaac Scott <isaac.scott@...asonboard.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Fabio Estevam <festevam@...il.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Liu Ying <victor.liu@....com>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Rob Herring <robh@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Shawn Guo <shawnguo@...nel.org>, Yannic Moog <y.moog@...tec.de>,
	devicetree@...r.kernel.org, imx@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1
 frequency to 506.8 MHz

On Thu, Oct 17, 2024 at 05:11:20AM +0200, Marek Vasut wrote:
> The LVDS panel on this device uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1
> to 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout engine can
> reach accurate pixel clock of exactly 72.4 MHz.
> 
> Without this patch, the Video PLL1 frequency is the default set in imx8mp.dtsi
> which is 1039.5 MHz, which divides down to inaccurate pixel clock of 74.25 MHz
> which works for this particular panel by sheer chance.
> 
> Stop taking that chance and set correct accurate pixel clock frequency instead.
> 
> Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support")
> Reported-by: Isaac Scott <isaac.scott@...asonboard.com>
> Signed-off-by: Marek Vasut <marex@...x.de>

Applied, thanks!