linux-kernel - Re: [PATCH 47/47] KVM: arm64: nv: Add trap forwarding for FEAT

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Message-ID: <8c14a3ca-2986-484f-9bc1-c2cf4aa08211@arm.com>
Date: Mon, 21 Oct 2024 09:31:42 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: Oliver Upton <oliver.upton@...ux.dev>
Cc: linux-kernel@...r.kernel.org, kvmarm@...ts.linux.dev,
 linux-arm-kernel@...ts.infradead.org, maz@...nel.org,
 James Morse <james.morse@....com>, Suzuki K Poulose
 <suzuki.poulose@....com>, Catalin Marinas <catalin.marinas@....com>,
 Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org>
Subject: Re: [PATCH 47/47] KVM: arm64: nv: Add trap forwarding for FEAT_FGT2
 described registers



On 10/4/24 10:31, Oliver Upton wrote:
> On Thu, Oct 03, 2024 at 09:46:08AM +0530, Anshuman Khandual wrote:
>>> I have a patch in the nested PMU series that uses a single complex trap
>>> ID to evaluate HPMN, and derives the index from ESR_EL2. I think it
>>> could also be extended to the PMEVCNTSVR<n> range as well.
>>
>> Just for reference - the mentioned complex trap ID function from the
>> given link below.
>>
>> static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu)
>> {
>> 	u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
>> 	u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
>> 	unsigned int idx;
>>
>>
>> 	switch (sysreg) {
>> 	case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30):
>> 	case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30):
>>
>> ---------------------------------------------------------------------
>> Just add the new system register range here ?
>>
>> +	case SYS_PMEVCNTSVR_EL1(0)... SYS_PMEVCNTSVR_EL1(31):
>> ---------------------------------------------------------------------
>>
>> 		idx = (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg);
>> 		break;
> 
> Yes, so long as the layout of encodings matches the established pattern
> for value / type registers (I haven't checked this).
> 
>>>
>>> Also, keep in mind that the HPMN trap is annoying since it affects Host
>>> EL0 in addition to 'guest' ELs.
>>
>> Does this require any more special handling other than the above complex trap
>> ID function ?
> 
> There's another patch in that series I linked that allows EL2 traps to
> describe behavior that takes effect in host EL0.
> 
> So I don't believe there's anything in particular related to HPMN that
> you need to evaluate. I wanted to mention it because some of the PMU
> related traps besides HPMN take effect in Host EL0, so do keep it in
> mind.
> 
> With that said, I haven't seen an FGT yet that applies to Host EL0.
> 

Hello Oliver,

Should I rebase this series on the latest series you have posted earlier this
month [1] ? Also wondering if you had a chance to look into other KVM patches
here ? Please do let me know if they too need any modification.

  KVM: arm64: nv: Add FEAT_FGT2 registers access from virtual EL2
  KVM: arm64: nv: Add FEAT_FGT2 registers based FGU handling
  KVM: arm64: nv: Add trap forwarding for FEAT_FGT2 described registers

[1] https://lore.kernel.org/kvmarm/20241007174559.1830205-1-oliver.upton@linux.dev/

- Anshuman