lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <SJ1PR11MB60834693031EB4CBA4BE7BFDFC432@SJ1PR11MB6083.namprd11.prod.outlook.com>
Date: Mon, 21 Oct 2024 17:59:24 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: Borislav Petkov <bp@...en8.de>
CC: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>, Thomas Gleixner
	<tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, Dave Hansen
	<dave.hansen@...ux.intel.com>, "x86@...nel.org" <x86@...nel.org>,
	"daniel.sneddon@...ux.intel.com" <daniel.sneddon@...ux.intel.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
	"linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>, "Josh
 Poimboeuf" <jpoimboe@...nel.org>, Srinivas Pandruvada
	<srinivas.pandruvada@...ux.intel.com>, "Rafael J. Wysocki"
	<rafael@...nel.org>, Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>,
	"Liang, Kan" <kan.liang@...ux.intel.com>, "andrew.cooper3@...rix.com"
	<andrew.cooper3@...rix.com>, Brice Goglin <brice.goglin@...il.com>, "Mario
 Limonciello" <mario.limonciello@....com>, Perry Yuan <Perry.Yuan@....com>,
	Dapeng Mi <dapeng1.mi@...ux.intel.com>
Subject: RE: [PATCH v4 02/10] x86/cpu/topology: Add CPU type to struct
 cpuinfo_topology

> > #define INTEL_ALDERLAKE_L               IFM(6, 0x9A) /* Golden Cove / Gracemont */
> >
> > #define INTEL_RAPTORLAKE                IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */
> >
> > The native model number could be helpful to tell what each of your P-cores and E-cores
> > are based on. Could be useful when the same base core is used in more than one SoC
> > generation.
>
> How am I supposed to read this?
>
> Gracemont is the "native", base core and from that they do a Golden Cove and
> a Raptor Cove?
>
> What does that have to do with the P- and E-cores? Are those above two
> different types wrt performance?

If you are running on an Alder Lake you'll see that CPUID says you are
family 6, model 9A. CPUID will also tell you that this is a hybrid part
with both P-cores and E-cores. CPUID will tell you which logical CPUs
are P-cores and which are E-cores.

But in some cases you might want to know *which* E-core you have
(likely cases are for performance counters). The native model number
will help with that.

We probably ought to publish a table of native model numbers ... but
I don't know if there are plans to do that. Likely that Wikipedia will get
to that before Intel does. 

-Tony

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ