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Message-ID: <SJ1PR11MB6083E463572AC9E110A7199FFC432@SJ1PR11MB6083.namprd11.prod.outlook.com>
Date: Mon, 21 Oct 2024 18:40:04 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: "Mehta, Sohil" <sohil.mehta@...el.com>, "Zhuo, Qiuxu"
	<qiuxu.zhuo@...el.com>
CC: "bp@...en8.de" <bp@...en8.de>, "tglx@...utronix.de" <tglx@...utronix.de>,
	"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
	"mingo@...hat.com" <mingo@...hat.com>, "hpa@...or.com" <hpa@...or.com>,
	"x86@...nel.org" <x86@...nel.org>, "linux-edac@...r.kernel.org"
	<linux-edac@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 06/10] x86/mce: Convert multiple if () statements into
 a switch() statement

>> Intel model number allocation policies aren't necessarily sequential.
>
> Model numbers are assumed to be sequential at least within family 6.

Assumption can only be applied retroactively to simpler times.  Looking
at the timelines and model numbers for pure-Atom, pure-Core, Hybrid,
and Xeon, they are somewhat jumbled.

> For example, does the following change from Qiuxu, unintentionally
> become applicable to Quark CPUs with family -> 5?

Qiuxu starts the function with:

+       /* Older CPUs don't need quirks. */
+       if (c->x86 < 6)
+               return;

So Quark leaves the function early.

-Tony

	

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