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Message-ID: <SJ1PR11MB6083740D3EAD10DCDCA12EE8FC432@SJ1PR11MB6083.namprd11.prod.outlook.com>
Date: Mon, 21 Oct 2024 23:31:04 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: "Mehta, Sohil" <sohil.mehta@...el.com>, "Zhuo, Qiuxu"
	<qiuxu.zhuo@...el.com>
CC: "bp@...en8.de" <bp@...en8.de>, "tglx@...utronix.de" <tglx@...utronix.de>,
	"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
	"mingo@...hat.com" <mingo@...hat.com>, "hpa@...or.com" <hpa@...or.com>,
	"x86@...nel.org" <x86@...nel.org>, "linux-edac@...r.kernel.org"
	<linux-edac@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 06/10] x86/mce: Convert multiple if () statements into
 a switch() statement

> Trying to understand more, I have more questions than answers. With the
> introduction of Family 0x19, do we need to reevaluate some of the
> existing model checks?

Diamond Rapids is in Family 19, not 0x19.  I was unsure in <asm/intel-family.h>
to use decimal or hex for family (since only 5 & 6 are used there, and they are
same in both bases). I picked decimal to avoid 0x prefixes everywhere.

> early_init_intel():
> if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
>     (c->x86 == 0x6 && c->x86_model >= 0x0e))
>       set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
>
> It seems "constant_tsc" wouldn't show on Diamond rapids. Do we need it to?

This looks to be checking for Pentium IV Prescott or newer in
family 0xf, or Yonah or newer in family 6.

You are right that it won't catch the new families. But it might
not matter if this later block sets the feature bit.

        /*
         * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
         * with P/T states and does not stop in deep C-states.
         *
         * It is also reliable across cores and sockets. (but not across
         * cabinets - we turn it off in that case explicitly.)
         */
        if (c->x86_power & (1 << 8)) {
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
                set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
        }

It appears that constant TSC started out model specific, but later
got a proper enumeration bit in CPUID.

-Tony


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