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Message-ID: <efdcdd4b-c5ca-42cc-beed-e92201bc07e9@linaro.org>
Date: Mon, 21 Oct 2024 14:21:44 +0200
From: neil.armstrong@...aro.org
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
 Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>
Cc: Johan Hovold <johan+linaro@...nel.org>, linux-arm-msm@...r.kernel.org,
 linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 4/6] phy: qualcomm: qmp-pcie: split PCS_LANE1 region

On 21/10/2024 12:33, Dmitry Baryshkov wrote:
> The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled
> this way as it simplified handled of devices with the old bindings.
> Nowadays it can be handled as is, without hacks.
> 
> Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c           | 32 ++++++++++++++++++----
>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h |  5 ++--
>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h |  5 ++--
>   3 files changed, 33 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 873f2f9844c66d7bd0b3bb3ab4bbd8be9a37cebd..1ca1f21b1cc225f435da9c775c97dfa142117f95 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -1773,7 +1773,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
>   	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
>   };
>   
> -static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {
> +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = {
>   	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
>   	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
>   };
> @@ -1907,6 +1907,9 @@ static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
> +};
> +
> +static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = {
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
>   };
> @@ -2582,8 +2585,6 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {
>   static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = {
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
> -	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
> -	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
>   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
>   };
> @@ -2728,6 +2729,7 @@ struct qmp_pcie_offsets {
>   	u16 serdes;
>   	u16 pcs;
>   	u16 pcs_misc;
> +	u16 pcs_lane1;
>   	u16 tx;
>   	u16 rx;
>   	u16 tx2;
> @@ -2752,6 +2754,8 @@ struct qmp_phy_cfg_tbls {
>   	int pcs_num;
>   	const struct qmp_phy_init_tbl *pcs_misc;
>   	int pcs_misc_num;
> +	const struct qmp_phy_init_tbl *pcs_lane1;
> +	int pcs_lane1_num;
>   	const struct qmp_phy_init_tbl *ln_shrd;
>   	int ln_shrd_num;
>   };
> @@ -2811,6 +2815,7 @@ struct qmp_pcie {
>   	void __iomem *serdes;
>   	void __iomem *pcs;
>   	void __iomem *pcs_misc;
> +	void __iomem *pcs_lane1;
>   	void __iomem *tx;
>   	void __iomem *rx;
>   	void __iomem *tx2;
> @@ -2927,6 +2932,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
>   	.serdes		= 0x1000,
>   	.pcs		= 0x1200,
>   	.pcs_misc	= 0x1600,
> +	.pcs_lane1	= 0x1e00,
>   	.tx		= 0x0000,
>   	.rx		= 0x0200,
>   	.tx2		= 0x0800,
> @@ -2957,6 +2963,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
>   	.serdes		= 0x1000,
>   	.pcs		= 0x1200,
>   	.pcs_misc	= 0x1400,
> +	.pcs_lane1	= 0x1e00,
>   	.tx		= 0x0000,
>   	.rx		= 0x0200,
>   	.tx2		= 0x0800,
> @@ -3440,8 +3447,8 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
>   	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
>   		.serdes		= sdx55_qmp_pcie_ep_serdes_tbl,
>   		.serdes_num	= ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
> -		.pcs_misc	= sdx55_qmp_pcie_ep_pcs_misc_tbl,
> -		.pcs_misc_num	= ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl),
> +		.pcs_lane1	= sdx55_qmp_pcie_ep_pcs_lane1_tbl,
> +		.pcs_lane1_num	= ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl),
>   	},
>   
>   	.reset_list		= sdm845_pciephy_reset_l,
> @@ -3540,6 +3547,8 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
>   			.pcs_num        = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),
>   			.pcs_misc       = sdx65_qmp_pcie_pcs_misc_tbl,
>   			.pcs_misc_num   = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
> +			.pcs_lane1       = sdx65_qmp_pcie_pcs_lane1_tbl,
> +			.pcs_lane1_num   = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
>   		},
>   	.reset_list             = sdm845_pciephy_reset_l,
>   	.num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
> @@ -3739,6 +3748,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
>   		.pcs_num		= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
>   		.pcs_misc		= sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
>   		.pcs_misc_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
> +		.pcs_lane1	= sdx65_qmp_pcie_pcs_lane1_tbl,
> +		.pcs_lane1_num	= ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
>   	},
>   
>   	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
> @@ -3945,6 +3956,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
>   	void __iomem *rx2 = qmp->rx2;
>   	void __iomem *pcs = qmp->pcs;
>   	void __iomem *pcs_misc = qmp->pcs_misc;
> +	void __iomem *pcs_lane1 = qmp->pcs_lane1;
>   	void __iomem *ln_shrd = qmp->ln_shrd;
>   
>   	if (!tbls)
> @@ -3969,6 +3981,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
>   
>   	qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
>   	qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
> +	qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num);
>   
>   	if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
>   		qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl,
> @@ -4420,6 +4433,14 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np
>   		}
>   	}
>   
> +	/*
> +	 * For all platforms where legacy bindings existed, PCS_LANE1 was
> +	 * mapped as a part of the PCS_MISC region.
> +	 */
> +	if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0)
> +		qmp->pcs_lane1 = qmp->pcs_misc +
> +			(cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc);
> +
>   	clk = devm_get_clk_from_child(dev, np, NULL);
>   	if (IS_ERR(clk)) {
>   		return dev_err_probe(dev, PTR_ERR(clk),
> @@ -4487,6 +4508,7 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
>   	qmp->serdes = base + offs->serdes;
>   	qmp->pcs = base + offs->pcs;
>   	qmp->pcs_misc = base + offs->pcs_misc;
> +	qmp->pcs_lane1 = base + offs->pcs_lane1;
>   	qmp->tx = base + offs->tx;
>   	qmp->rx = base + offs->rx;
>   
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
> index ac872a9eff9a8fe7fc3307759288aee15d17bd24..ab892d1067c219e8db0ba0591921b38a9cebebe7 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
> @@ -13,7 +13,8 @@
>   #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME		0x0f4
>   #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2		0x0fc
>   #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5		0x108
> -#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2		0x824
> -#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2		0x828
> +
> +#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2		0x024
> +#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2		0x028
>   
>   #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
> index cdf8c04ea078a985be82d561ad0918dfdece9987..283d63c8159338b57a5026b6c2a86e3cce21097c 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
> @@ -17,7 +17,8 @@
>   #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5		0x108
>   #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN			0x15c
>   #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3	0x184
> -#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2		0xa24
> -#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2		0xa28
> +
> +#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2		0x024
> +#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2		0x028
>   
>   #endif
> 

Looks good

Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>

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