linux-kernel - Re: [PATCH v1 02/10] media: platform: mediatek: add seninf controller

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Message-ID: <f7c19ef542f1f86c6ecf355942a6e7934e543c97.camel@mediatek.com>
Date: Tue, 22 Oct 2024 04:16:17 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: "sumit.semwal@...aro.org" <sumit.semwal@...aro.org>,
	"christian.koenig@....com" <christian.koenig@....com>, "mchehab@...nel.org"
	<mchehab@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
	"robh@...nel.org" <robh@...nel.org>, "matthias.bgg@...il.com"
	<matthias.bgg@...il.com>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	Shu-hsiang Yang (楊舒翔)
	<Shu-hsiang.Yang@...iatek.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	"yunkec@...omium.org" <yunkec@...omium.org>, "linaro-mm-sig@...ts.linaro.org"
	<linaro-mm-sig@...ts.linaro.org>, "linux-media@...r.kernel.org"
	<linux-media@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, Yaya Chang (張雅清)
	<Yaya.Chang@...iatek.com>, Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@...iatek.com>,
	"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	Teddy Chen (陳乾元) <Teddy.Chen@...iatek.com>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "hidenorik@...omium.org"
	<hidenorik@...omium.org>, Shun-Yi Wang (王順億)
	<Shun-Yi.Wang@...iatek.com>
Subject: Re: [PATCH v1 02/10] media: platform: mediatek: add seninf controller

Hi, Shu-hsiang:

On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces support for the sensor interface in the MediaTek SoC,
> with the focus on CSI and stream control. The key functionalities
> include parameter control, metering and maintaining status information,
> interrupt handling, and debugging. These features ensure effective
> management and debugging of the camera sensor interface hardware.
> 
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@...iatek.com>
> ---

[snip]

> +int mtk_cam_seninf_init_iomem(struct seninf_ctx *ctx, void __iomem *if_base,
> +			      void __iomem *ana_base)
> +{

This function is defined in this patch but only used by patch [3/10].
There are many function defined in this patch but used only in patch [3/10].
I think this patch and patch [3/10] should be merged into one patch which is a complete sensor interface driver.
To prevent this patch to be too big, separate advanced function to another patches.

Regards,
CK

> +	u32 i;
> +
> +	ctx->reg_ana_csi_rx[CSI_PORT_0] =
> +	ctx->reg_ana_csi_rx[CSI_PORT_0A] = ana_base + 0;
> +	ctx->reg_ana_csi_rx[CSI_PORT_0B] = ana_base + 0x1000;
> +
> +	ctx->reg_ana_csi_rx[CSI_PORT_1] =
> +	ctx->reg_ana_csi_rx[CSI_PORT_1A] = ana_base + 0x4000;
> +	ctx->reg_ana_csi_rx[CSI_PORT_1B] = ana_base + 0x5000;
> +
> +	ctx->reg_ana_csi_rx[CSI_PORT_2] =
> +	ctx->reg_ana_csi_rx[CSI_PORT_2A] = ana_base + 0x8000;
> +	ctx->reg_ana_csi_rx[CSI_PORT_2B] = ana_base + 0x9000;
> +
> +	ctx->reg_ana_csi_rx[CSI_PORT_3] =
> +	ctx->reg_ana_csi_rx[CSI_PORT_3A] = ana_base + 0xc000;
> +	ctx->reg_ana_csi_rx[CSI_PORT_3B] = ana_base + 0xd000;
> +
> +	ctx->reg_ana_dphy_top[CSI_PORT_0A] =
> +	ctx->reg_ana_dphy_top[CSI_PORT_0B] =
> +	ctx->reg_ana_dphy_top[CSI_PORT_0] = ana_base + 0x2000;
> +
> +	ctx->reg_ana_dphy_top[CSI_PORT_1A] =
> +	ctx->reg_ana_dphy_top[CSI_PORT_1B] =
> +	ctx->reg_ana_dphy_top[CSI_PORT_1] = ana_base + 0x6000;
> +
> +	ctx->reg_ana_dphy_top[CSI_PORT_2A] =
> +	ctx->reg_ana_dphy_top[CSI_PORT_2B] =
> +	ctx->reg_ana_dphy_top[CSI_PORT_2] = ana_base + 0xa000;
> +
> +	ctx->reg_ana_dphy_top[CSI_PORT_3A] =
> +	ctx->reg_ana_dphy_top[CSI_PORT_3B] =
> +	ctx->reg_ana_dphy_top[CSI_PORT_3] = ana_base + 0xe000;
> +
> +	ctx->reg_ana_cphy_top[CSI_PORT_0A] =
> +	ctx->reg_ana_cphy_top[CSI_PORT_0B] =
> +	ctx->reg_ana_cphy_top[CSI_PORT_0] = ana_base + 0x3000;
> +
> +	ctx->reg_ana_cphy_top[CSI_PORT_1A] =
> +	ctx->reg_ana_cphy_top[CSI_PORT_1B] =
> +	ctx->reg_ana_cphy_top[CSI_PORT_1] = ana_base + 0x7000;
> +
> +	ctx->reg_ana_cphy_top[CSI_PORT_2A] =
> +	ctx->reg_ana_cphy_top[CSI_PORT_2B] =
> +	ctx->reg_ana_cphy_top[CSI_PORT_2] = ana_base + 0xb000;
> +
> +	ctx->reg_ana_cphy_top[CSI_PORT_3A] =
> +	ctx->reg_ana_cphy_top[CSI_PORT_3B] =
> +	ctx->reg_ana_cphy_top[CSI_PORT_3] = ana_base + 0xf000;
> +
> +	ctx->reg_if_top = if_base;
> +
> +	for (i = SENINF_1; i < _seninf_cfg.seninf_num; i++) {
> +		ctx->reg_if_ctrl[i] = if_base + 0x0200 + (0x1000 * i);
> +		ctx->reg_if_tg[i] = if_base + 0x0F00 + (0x1000 * i);
> +		ctx->reg_if_csi2[i] = if_base + 0x0a00 + (0x1000 * i);
> +	}
> +
> +	for (i = SENINF_MUX1; i < _seninf_cfg.mux_num; i++)
> +		ctx->reg_if_mux[i] = if_base + 0x0d00 + (0x1000 * i);
> +
> +	ctx->reg_if_cam_mux = if_base + 0x0400;
> +
> +	return 0;
> +}
> +