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Message-ID: <7btps7egaaxz5wguakki3qs6aorv2ujhjgirrkgmdx42rpjqgc@qzzjb7ijb6bh>
Date: Tue, 22 Oct 2024 19:24:54 -0700
From: Davidlohr Bueso <dave@...olabs.net>
To: shiju.jose@...wei.com
Cc: dave.jiang@...el.com, dan.j.williams@...el.com, 
	jonathan.cameron@...wei.com, alison.schofield@...el.com, vishal.l.verma@...el.com, 
	ira.weiny@...el.com, linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linuxarm@...wei.com, tanxiaofei@...wei.com, prime.zeng@...ilicon.com
Subject: Re: [PATCH v2 4/6] cxl/events: Update DRAM Event Record to CXL spec
 rev 3.1

On Tue, 22 Oct 2024, shiju.jose@...wei.com wrote:\n
>From: Shiju Jose <shiju.jose@...wei.com>
>
>CXL spec 3.1 section 8.2.9.2.1.2 Table 8-46, DRAM Event Record has updated
>with following new fields and new types for Memory Event Type, Transaction
>Type and Validity Flags fields.
>1. Component Identifier
>2. Sub-channel
>3. Advanced Programmable Corrected Memory Error Threshold Event Flags
>4. Corrected Memory Error Count at Event
>5. Memory Event Sub-Type
>
>Update DRAM events record and DRAM trace event for the above spec
>changes. The new fields are inserted in logical places.
>Includes trivial consistency of white space improvements.

Reviewed-by: Davidlohr Bueso <dave@...olabs.net>

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