linux-kernel - RE: [PATCH v7 4/5] x86/mce/apei: Handle variable register array size

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Message-ID: <CY8PR11MB713447591D1C8BC77F39118C894E2@CY8PR11MB7134.namprd11.prod.outlook.com>
Date: Thu, 24 Oct 2024 05:25:48 +0000
From: "Zhuo, Qiuxu" <qiuxu.zhuo@...el.com>
To: Avadhut Naik <avadhut.naik@....com>, "x86@...nel.org" <x86@...nel.org>,
	"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
	"linux-trace-kernel@...r.kernel.org" <linux-trace-kernel@...r.kernel.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"bp@...en8.de" <bp@...en8.de>, "Luck, Tony" <tony.luck@...el.com>,
	"tglx@...utronix.de" <tglx@...utronix.de>, "mingo@...hat.com"
	<mingo@...hat.com>, "rostedt@...dmis.org" <rostedt@...dmis.org>,
	"mchehab@...nel.org" <mchehab@...nel.org>, "yazen.ghannam@....com"
	<yazen.ghannam@....com>, "john.allen@....com" <john.allen@....com>
Subject: RE: [PATCH v7 4/5] x86/mce/apei: Handle variable register array size

> From: Avadhut Naik <avadhut.naik@....com>
> Sent: Wednesday, October 23, 2024 3:37 AM
> To: x86@...nel.org; linux-edac@...r.kernel.org; linux-trace-
> kernel@...r.kernel.org
> Cc: linux-kernel@...r.kernel.org; bp@...en8.de; Luck, Tony
> <tony.luck@...el.com>; Zhuo, Qiuxu <qiuxu.zhuo@...el.com>;
> tglx@...utronix.de; mingo@...hat.com; rostedt@...dmis.org;
> mchehab@...nel.org; yazen.ghannam@....com; john.allen@....com;
> avadhut.naik@....com
> Subject: [PATCH v7 4/5] x86/mce/apei: Handle variable register array size
> 
> From: Yazen Ghannam <yazen.ghannam@....com>
> 
> ACPI Boot Error Record Table (BERT) is being used by the kernel to report
> errors that occurred in a previous boot. On some modern AMD systems,
> these very errors within the BERT are reported through the
> x86 Common Platform Error Record (CPER) format which consists of one or
> more Processor Context Information Structures. These context structures
> provide a starting address and represent an x86 MSR range in which the data
> constitutes a contiguous set of MSRs starting from, and including the starting
> address.
> 
> It's common, for AMD systems that implement this behavior, that the MSR
> range represents the MCAX register space used for the Scalable MCA feature.
> The apei_smca_report_x86_error() function decodes and passes this
> information through the MCE notifier chain. However, this function assumes
> a fixed register size based on the original HW/FW implementation.
> 
> This assumption breaks with the addition of two new MCAX registers viz.
> MCA_SYND1 and MCA_SYND2. These registers are added at the end of the
> MCAX register space, so they won't be included when decoding the CPER
> data.
> 
> Rework apei_smca_report_x86_error() to support a variable register array
> size. This covers any case where the MSR context information starts at the
> MCAX address for MCA_STATUS and ends at any other register within the
> MCAX register space.
> 
> Add code comments indicating the MCAX register at each offset.
> 
> [Yazen: Add Avadhut as co-developer for wrapper changes.]
> 
> Co-developed-by: Avadhut Naik <avadhut.naik@....com>
> Signed-off-by: Avadhut Naik <avadhut.naik@....com>
> Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>
> Signed-off-by: Avadhut Naik <avadhut.naik@....com>

LGTM.

    Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@...el.com>