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Message-ID: <50874428-b4ef-4e65-b60b-1bd917f1933c@redhat.com>
Date: Thu, 24 Oct 2024 10:26:01 +0200
From: Paolo Abeni <pabeni@...hat.com>
To: Jijie Shao <shaojijie@...wei.com>, davem@...emloft.net,
edumazet@...gle.com, kuba@...nel.org, shenjian15@...wei.com,
salil.mehta@...wei.com
Cc: liuyonglong@...wei.com, wangpeiyang1@...wei.com, lanhao@...wei.com,
chenhao418@...wei.com, netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 net 1/9] net: hns3: default enable tx bounce buffer
when smmu enabled
On 10/18/24 12:10, Jijie Shao wrote:
> From: Peiyang Wang <wangpeiyang1@...wei.com>
>
> The SMMU engine on HIP09 chip has a hardware issue.
> SMMU pagetable prefetch features may prefetch and use a invalid PTE
> even the PTE is valid at that time. This will cause the device trigger
> fake pagefaults. The solution is to avoid prefetching by adding a
> SYNC command when smmu mapping a iova. But the performance of nic has a
> sharp drop. Then we do this workaround, always enable tx bounce buffer,
> avoid mapping/unmapping on TX path.
>
> This issue only affects HNS3, so we always enable
> tx bounce buffer when smmu enabled to improve performance.
>
> Signed-off-by: Peiyang Wang <wangpeiyang1@...wei.com>
> Signed-off-by: Jian Shen <shenjian15@...wei.com>
> Signed-off-by: Jijie Shao <shaojijie@...wei.com>
I'm sorry to nick pick on somewhat small details, but we really need a
fixes tag here to make 110% clear is a bugfix. I guess it could be the
commit introducing the support for the buggy H/W.
Thanks,
Paolo
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