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Message-ID: <641f830e-8d21-4bc0-abe2-59e2c4d29b92@quicinc.com>
Date: Thu, 24 Oct 2024 18:55:42 +0530
From: Kiran Kumar C.S.K <quic_kkumarcs@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>
CC: "Russell King (Oracle)" <linux@...linux.org.uk>, <netdev@...r.kernel.org>,
Andy Gross <agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
"David S. Miller"
<davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
<kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, Rob Herring
<robh+dt@...nel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Jacob Keller
<jacob.e.keller@...el.com>,
Bhupesh Sharma <bhupesh.sharma@...aro.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <vsmuthu@....qualcomm.com>,
<arastogi@....qualcomm.com>, <linchen@....qualcomm.com>,
<john@...ozen.org>, Luo Jie <quic_luoj@...cinc.com>,
Pavithra R <quic_pavir@...cinc.com>,
"Suruchi Agarwal (QUIC)" <quic_suruchia@...cinc.com>,
"Lei Wei (QUIC)"
<quic_leiwei@...cinc.com>
Subject: Re: RFC: Advice on adding support for Qualcomm IPQ9574 SoC Ethernet
On 10/22/2024 7:07 PM, Andrew Lunn wrote:
>> Apologies for the delay in response. I understand that the PCS<->PHY
>> clocks may be out of the scope of PCS DT due to the reasons you mention.
>> However would like to clarify that the MII clocks referred to here, are
>> part of the connection between the MAC and PCS and not between PCS and PHY.
>>
>> Below is a diagram that shows the sub-blocks inside the 'UNIPHY' block
>> of IPQ9574 which houses the PCS and the serdes, along with the clock
>> connectivity. The MII Rx/Tx clocks are supplied from the NSS CC, to the
>> GMII channels between PCS and MAC. So, it seemed appropriate to have
>> these clocks described as part of the PCS DT node.
>>
>> +-------+ +---------+ +-------------------------+
>> -----------|CMN PLL| | GCC | | NSSCC (Divider) |
>> |25/50mhz +----+--+ +----+----+ +--+-------+--------------+
>> |clk | | ^ |
>> | 31.25M | SYS/AHB|clk RX/TX|clk +------------+
>> | ref clk | | | | |
>> | | v | MII RX|TX clk MAC| RX/TX clk
>> | +--+---------+----------+-------+---+ +-+---------+
>> | | | +----------------+ | | | | PPE |
>> v | | | UNIPHY0 V | | V |
>> +-------+ | v | +-----------+ (X)GMII| | |
>> | | | +---+---+ | |--------|------|-- MAC0 |
>> | | | | | | | (X)GMII| | |
>> | Quad | | |SerDes | | (X)PCS |--------|------|-- MAC1 |
>> | +<----+ | | | | (X)GMII| | |
>> |(X)GPHY| | | | | |--------|------|-- MAC2 |
>> | | | | | | | (X)GMII| | |
>> | | | +-------+ | |--------|------|-- MAC3 |
>> +-------+ | | | | | |
>> | +-----------+ | | |
>> +-----------------------------------+ | |
>
> Thanks for the detailed diagram. That always helps get things
> straight.
>
> Im i correct in says that MII RX|TX is identical to MAC RX|TX? These
> two clocks are used by the MAC and XPCS to clock data from one to the
> other? If they are the exact same clocks, i would suggest you use the
> same name, just to avoid confusion.
>
Yes, these two clocks are used by MAC and PCS to clock data to one
another. The MAC Rx/Tx clocks and MII Rx/Tx clocks are different clocks
and can be enabled/disabled independently. However their parent clock is
the same and hence their rate is same at all times. For example, the
phylink ops will set the rate of MAC Rx/Tx during a link speed change,
and this same rate is effected for the MII Rx/Tx clock.
Sure for the purpose of rest of this discussion, we can refer to them as
MII Rx/Tx clocks.
I would also like to clarify that each of the '(X)PCS' blocks shown in
the diagram, includes two PCS types, a 'PCS' type that supports 1Gbps
PCS modes, and another 'XPCS' block (Synopsys) that supports 10Gbps PCS
modes. The MII Rx/Tx clocks from the NSS CC, are supplied to the xGMII
channels of both these PCS.
> Both XPCS and PPE are clock consumers, so both will have a phandle
> pointing to the NSSCC clock provider?
>
Yes, this is correct.
>> We had one other question on the approach used in the driver for PCS
>> clocks, could you please provide your comments.
>>
>> As we can see from the above diagram, each serdes in the UNIPHY block
>> provides the clocks to the NSSCC, and the PCS block consumes the MII
>> Rx/Tx clocks. In our current design, the PCS/UNIPHY driver registers a
>> provider driver for the clocks that the serdes supplies to the NSS CC.
>
> That sounds reasonable>
>> It also enables the MII Rx/Tx clocks which are supplied to the PCS from
>> the NSS CC. Would this be an acceptable design to have the PCS driver
>> register the clock provider driver and also consume the MII Rx/Tx
>> clocks? It may be worth noting that the serdes and PCS are part of the
>> same UNIPHY block and also share same register region.
>
> Does the SERDES consume the MII Rx/Tx? Your diagram indicates it does
> not.
The SERDES in the UNIPHY does not consume the MII Rx/Tx clocks. The
consumer of these clocks is the PCS block within the UNIPHY.
The SERDES only provides the source Rx/tx clocks to the NSS CC, and the
NSS CC divides this clock and supplies the per-channel MII Rx/Tx clocks
to the PCS.
> I'm just wondering if you have circular dependencies at runtime?
>
> Where you will need to be careful is probe time vs runtime. Since you
> have circular phandles you need to first create all the clock
> providers, and only then start the clock consumers. Otherwise you
> might get into an endless EPROBE_DEFER loop.
>
The Rx/Tx clocks sourced from the SERDES are registered as provider
clocks by the UNIPHY/PCS driver during probe time. There is no runtime
operation needed for these clocks after this.
The MII Rx/Tx clocks are enabled later when the MAC is initialized by
the network driver. The network driver calls an API exported by the PCS
driver, which creates the PCS instance and enables the MII Rx/Tx clocks.
Ideally, the PCS driver probe should have completed and provider clocks
registered, by the time the MAC is initialized (we handle the error case
in case the probe is still not complete).
> Andrew
>
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