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Message-ID: <c81b26dc-1c52-42b6-ba68-95906b9c524c@oss.qualcomm.com>
Date: Fri, 25 Oct 2024 19:46:08 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Song Xue <quic_songxue@...cinc.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: kernel@...cinc.com, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: qcs615: Add LLCC support for QCS615

On 11.10.2024 12:41 PM, Song Xue wrote:
> The QCS615 platform has LLCC(Last Level Cache Controller) as the system
> cache controller. It includes 1 LLCC instance and 1 LLCC broadcast
> interface.
> 
> Add LLCC node support for the QCS615 platform.
> 
> Signed-off-by: Song Xue <quic_songxue@...cinc.com>
> ---
> This patch series depends on below patch series:
> https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com/
> https://lore.kernel.org/linux-arm-msm/20241010-add_llcc_support_for_qcs615-v2-1-044432450a75@quicinc.com/
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index ac4c4c751da1fbb28865877555ba317677bc6bd2..b718a4d2270d64ed43c2eca078bfe52b78ff680c 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -495,6 +495,14 @@ dc_noc: interconnect@...0000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> +		llcc: system-cache-controller@...0000 {
> +			compatible = "qcom,qcs615-llcc";
> +			reg = <0x0 0x9200000 0x0 0x50000>,
> +			      <0x0 0x9600000 0x0 0x50000>;

Please pad both addresses to 8 hex digits (e.g. 0x09200000)

With that:

Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Konrad

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