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Message-Id: <20241026-sar2130p-llcc-v3-2-2a58fa1b4d12@linaro.org>
Date: Sat, 26 Oct 2024 18:43:32 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Conor Dooley <conor@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: [PATCH v3 2/3] soc: qcom: llcc: use deciman integers for bit shift
values
As pointed out by Konrad Dybcio, we generally should be using decimal
numbers to represent bit positions / bit shifts rather than hex numbers.
Use decimals for consistency.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
---
drivers/soc/qcom/llcc-qcom.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index a470285f54a875bf2262aac7b0f84ed8fd028ef1..891efd008b8e3d8b851ccf19d91e508b7a7bff40 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -27,14 +27,14 @@
#define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
#define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
#define ACT_CTRL_ACT_TRIG BIT(0)
-#define ACT_CTRL_OPCODE_SHIFT 0x01
-#define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
-#define ATTR1_FIXED_SIZE_SHIFT 0x03
-#define ATTR1_PRIORITY_SHIFT 0x04
-#define ATTR1_MAX_CAP_SHIFT 0x10
+#define ACT_CTRL_OPCODE_SHIFT 1
+#define ATTR1_PROBE_TARGET_WAYS_SHIFT 2
+#define ATTR1_FIXED_SIZE_SHIFT 3
+#define ATTR1_PRIORITY_SHIFT 4
+#define ATTR1_MAX_CAP_SHIFT 16
#define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
-#define ATTR0_BONUS_WAYS_SHIFT 0x10
+#define ATTR0_BONUS_WAYS_SHIFT 16
#define LLCC_STATUS_READ_DELAY 100
#define CACHE_LINE_SIZE_SHIFT 6
--
2.39.5
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