linux-kernel - Re: [PATCH v2] mediatek: dsi: Correct calculation formula of PHY Timing

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20241027143219.56e7b4d0@schleppi.lan>
Date: Sun, 27 Oct 2024 14:32:19 +0100
From: Jens Ziller <zillerbaer@....de>
To: Shuijing Li <shuijing.li@...iatek.com>
Cc: <chunkuang.hu@...nel.org>, <p.zabel@...gutronix.de>,
 <airlied@...il.com>, <daniel@...ll.ch>, <matthias.bgg@...il.com>,
 <angelogioacchino.delregno@...labora.com>, <jitao.shi@...iatek.com>,
 <dri-devel@...ts.freedesktop.org>, <linux-mediatek@...ts.infradead.org>,
 <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
 <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH v2] mediatek: dsi: Correct calculation formula of PHY
 Timing


Am Fri, 12 Apr 2024 11:11:39 +0800
schrieb Shuijing Li <shuijing.li@...iatek.com>:

> This patch correct calculation formula of PHY timing.
> The spec define HS-PREPARE should be from 40ns+4*UI(44ns) to
> 85ns+6*UI(91ns). But current duration is 88ns and is near the
> boundary. So this patch make the duration to 64ns so it is near the
> safe range.

Hi Shuijing,

with this patch the panel in the Tentacruel ASUS Chromebook CM14
(CM1402F) flickers. There are 1 or 2 times per second a black panel.
Stable Kernel 6.11.5 and mainline 6.12-rc4 works only when I reverse
this patch. There's a bug inside. Can you please check that?

Best regards
Jens

>
> Signed-off-by: Shuijing Li <shuijing.li@...iatek.com>
> ---
> Changes in v2:
> Add a commit to describe the improvements to this patch in detail,
> per suggestion frome previous thread:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20240315072945.19502-1-shuijing.li@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_dsi.c | 33
> +++++++++++++++--------------- 1 file changed, 17 insertions(+), 16
> deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c index a2fdfc8ddb15..d1bd7d671880
> 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -235,22 +235,23 @@ static void mtk_dsi_phy_timconfig(struct
> mtk_dsi *dsi) u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate,
> 1000000); struct mtk_phy_timing *timing = &dsi->phy_timing;
>
> -	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
> -	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) /
> 8000;
> -	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) /
> 8000 + 1 -
> -			     timing->da_hs_prepare;
> -	timing->da_hs_trail = timing->da_hs_prepare + 1;
> -
> -	timing->ta_go = 4 * timing->lpx - 2;
> -	timing->ta_sure = timing->lpx + 2;
> -	timing->ta_get = 4 * timing->lpx;
> -	timing->da_hs_exit = 2 * timing->lpx + 1;
> -
> -	timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
> -	timing->clk_hs_post = timing->clk_hs_prepare + 8;
> -	timing->clk_hs_trail = timing->clk_hs_prepare;
> -	timing->clk_hs_zero = timing->clk_hs_trail * 4;
> -	timing->clk_hs_exit = 2 * timing->clk_hs_trail;
> +	timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1;
> +	timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) /
> 8000 + 1;
> +	timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) /
> 8000 + 1 -
> +		timing->da_hs_prepare;
> +	timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000
> + 1; +
> +	timing->ta_go = 4 * timing->lpx;
> +	timing->ta_sure = 3 * timing->lpx / 2;
> +	timing->ta_get = 5 * timing->lpx;
> +	timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
> +
> +	timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) +
> 1;
> +	timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) /
> 8000 + 1;
> +	timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) /
> 8000 + 1;
> +	timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1
> -
> +		timing->clk_hs_prepare;
> +	timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
>
>  	timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
>  		  timing->da_hs_zero << 16 | timing->da_hs_trail <<
> 24;