linux-kernel - Re: [PATCH 06/11] clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver

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Message-ID: <1eaa1fc6-721c-46fd-bcc8-9b575d083dea@quicinc.com>
Date: Wed, 30 Oct 2024 23:28:36 +0530
From: Taniya Das <quic_tdas@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Abhishek Sahu
	<absahu@...eaurora.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Catalin Marinas
	<catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, Ajit Pandey
	<quic_ajipan@...cinc.com>,
        Imran Shaik <quic_imrashai@...cinc.com>,
        "Jagadeesh Kona" <quic_jkona@...cinc.com>,
        Stephen Boyd
	<sboyd@...eaurora.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 06/11] clk: qcom: dispcc-qcs615: Add QCS615 display clock
 controller driver



On 10/19/2024 1:55 AM, Dmitry Baryshkov wrote:
>> #include "common.h"
>> +#include "gdsc.h"
>> +#include "reset.h"
>> +
>> +enum {
>> +	DT_BI_TCXO,
>> +	DT_GPLL0,
>> +	DT_DSI0_PHY_PLL_OUT_BYTECLK,
>> +	DT_DSI0_PHY_PLL_OUT_DSICLK,
>> +	DT_DSI1_PHY_PLL_OUT_DSICLK,
> Is there a DSI 1 PLL on this platform?

As per the design of the clock controller it has a DSI1 port.

-- 
Thanks & Regards,
Taniya Das.