linux-kernel - Re: [PATCH v7 6/7] PCI: qcom: Disable ASPM L0s and remove BDF2SID mapping config for X1E80100 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <250bce05-a095-4eb3-a445-70bbf4366526@quicinc.com>
Date: Wed, 30 Oct 2024 13:54:59 +0800
From: Qiang Yu <quic_qianyu@...cinc.com>
To: Johan Hovold <johan@...nel.org>
CC: <manivannan.sadhasivam@...aro.org>, <vkoul@...nel.org>,
        <kishon@...nel.org>, <robh@...nel.org>, <andersson@...nel.org>,
        <konradybcio@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <mturquette@...libre.com>, <sboyd@...nel.org>, <abel.vesa@...aro.org>,
        <quic_msarkar@...cinc.com>, <quic_devipriy@...cinc.com>,
        <dmitry.baryshkov@...aro.org>, <kw@...ux.com>, <lpieralisi@...nel.org>,
        <neil.armstrong@...aro.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-phy@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <johan+linaro@...nel.org>,
        <stable@...r.kernel.org>
Subject: Re: [PATCH v7 6/7] PCI: qcom: Disable ASPM L0s and remove BDF2SID
 mapping config for X1E80100 SoC


On 10/24/2024 2:42 PM, Qiang Yu wrote:
>
> On 10/18/2024 10:06 PM, Johan Hovold wrote:
>> Please use a more concise subject (e.g. try to stay within 72 chars)
>> than:
>>
>>     PCI: qcom: Disable ASPM L0s and remove BDF2SID mapping config for 
>> X1E80100 SoC
>>
>> Here you could drop "SoC", maybe "ASPM" and "config" for example.
>>
>> On Wed, Oct 16, 2024 at 08:04:11PM -0700, Qiang Yu wrote:
>>> Currently, the cfg_1_9_0 which is being used for X1E80100 has 
>>> config_sid
>>> callback in its ops and doesn't disable ASPM L0s. However, as same as
>>> SC8280X, PCIe controllers on X1E80100 are connected to SMMUv3, hence 
>>> don't
>>> need config_sid() callback and hardware team has recommended to disable
>>> L0s as it is broken in the controller. Hence reuse cfg_sc8280xp for
>>> X1E80100.
>> Since the x1e80100 dtsi, like sc8280xp, do not specify an iommu-map,
>> that bit is effectively just a cleanup and all this patch does is to
>> disable L0s.
>>
>> Please rephrase to make this clear. This will also allow you to make the
>> Subject even shorter (no need to mention the SID bit in Subject).
>>
>> Also say something about how L0s is broken so that it is more clear what
>> the effect of this patch is. On sc8280xp enabling L0s lead to
>> correctable errors for example.
> Need more time to confirm the exact reason about disabling L0s.
> Will update if get any progress
Hi Johan Hovold

I confirmed with HW team and SW team. L0s is not supported on X1E80100, 
it is not fully verified. So we don't want to enable it.

Thanks,
Qiang Yu
>
> Thanks,
> Qiang
>>
>>> Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support")
>>> Cc: stable@...r.kernel.org
>> Johan