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Message-ID: <58e5dbbf-7c35-49ae-b2ff-954fc0e3fe48@quicinc.com>
Date: Wed, 30 Oct 2024 15:56:42 +0800
From: Qiang Yu <quic_qianyu@...cinc.com>
To: Johan Hovold <johan@...nel.org>,
Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>
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Subject: Re: [PATCH v7 6/7] PCI: qcom: Disable ASPM L0s and remove BDF2SID
mapping config for X1E80100 SoC
On 10/30/2024 3:42 PM, Johan Hovold wrote:
> On Wed, Oct 30, 2024 at 12:48:51PM +0530, Manivannan Sadhasivam wrote:
>> On Wed, Oct 30, 2024 at 08:15:05AM +0100, Johan Hovold wrote:
>>> Also, are there any Qualcomm platforms that actually support L0s?
>>> Perhaps we should just disable it everywhere?
>> Most of the mobile chipsets from Qcom support L0s. It is not supported only on
>> the compute ones. So we cannot disable it everywhere.
>>
>> Again, it is not the hw issue but the PHY init sequence not tuned support L0s.
> Right, this should be mentioned in the commit message.
OK, I got it. Will write this into commit message.
Thanks,
Qiang Yu
>
> Johan
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