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Message-ID: <20241031212511.57ec5d6e@jic23-huawei>
Date: Thu, 31 Oct 2024 21:25:11 +0000
From: Jonathan Cameron <jic23@...nel.org>
To: Angelo Dureghello <angelo@...nel-space.org>
Cc: Lars-Peter Clausen <lars@...afoo.de>, Michael Hennerich
 <Michael.Hennerich@...log.com>, Nuno Sá <nuno.sa@...log.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Olivier Moysan
 <olivier.moysan@...s.st.com>, linux-iio@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 dlechner@...libre.com, Mark Brown <broonie@...nel.org>, Angelo Dureghello
 <adureghello@...libre.com>
Subject: Re: [PATCH v9 7/8] iio: dac: ad3552r: add high-speed platform
 driver

On Mon, 28 Oct 2024 22:45:34 +0100
Angelo Dureghello <angelo@...nel-space.org> wrote:

> From: Angelo Dureghello <adureghello@...libre.com>
> 
> Add High Speed ad3552r platform driver.
> 
> The ad3552r DAC is controlled by a custom (fpga-based) DAC IP
> through the current AXI backend, or similar alternative IIO backend.
> 
> Compared to the existing driver (ad3552r.c), that is a simple SPI
> driver, this driver is coupled with a DAC IIO backend that finally
> controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach
> maximum transfer rate of 33MUPS using dma stream capabilities.
> 
> All commands involving QSPI bus read/write are delegated to the backend
> through the provided APIs for bus read/write.
> 
> Reviewed-by: Nuno Sa <nuno.sa@...log.com>
> Signed-off-by: Angelo Dureghello <adureghello@...libre.com>
Missing bitfield.h include. I added whilst applying.

Jonathan

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