linux-kernel - Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature

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Message-ID: <05c12dec-3f39-4811-8e15-82cfd229b66a@intel.com>
Date: Thu, 31 Oct 2024 16:11:51 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Amit Shah <amit@...nel.org>, linux-kernel@...r.kernel.org,
 kvm@...r.kernel.org, x86@...nel.org, linux-doc@...r.kernel.org
Cc: amit.shah@....com, thomas.lendacky@....com, bp@...en8.de,
 tglx@...utronix.de, peterz@...radead.org, jpoimboe@...nel.org,
 pawan.kumar.gupta@...ux.intel.com, corbet@....net, mingo@...hat.com,
 dave.hansen@...ux.intel.com, hpa@...or.com, seanjc@...gle.com,
 pbonzini@...hat.com, daniel.sneddon@...ux.intel.com, kai.huang@...el.com,
 sandipan.das@....com, boris.ostrovsky@...cle.com, Babu.Moger@....com,
 david.kaplan@....com
Subject: Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature

On 10/31/24 08:39, Amit Shah wrote:
...
> With the Enhanced Return Address Prediction Security feature,  any
> hardware TLB flush results in flushing of the RSB (aka RAP in AMD spec).
> This guarantees an RSB flush across context switches. 

Check out the APM, volume 2: "5.5.1 Process Context Identifier"

	... when system software switches address spaces (by writing ...
	CR3[62:12]), the processor may use TLB mappings previously
	stored for that address space and PCID, providing that bit 63 of
	the source operand is set to 1.

tl;dr: PCIDs mean you don't necessarily flush the TLB on context switches.