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Message-ID: <bbc3dfd40ab27bd6badbafddd88d10cbe29fd536.camel@amd.com>
Date: Mon, 4 Nov 2024 15:00:19 +0000
From: "Shah, Amit" <Amit.Shah@....com>
To: "andrew.cooper3@...rix.com" <andrew.cooper3@...rix.com>
CC: "corbet@....net" <corbet@....net>, "boris.ostrovsky@...cle.com"
	<boris.ostrovsky@...cle.com>, "kai.huang@...el.com" <kai.huang@...el.com>,
	"jpoimboe@...nel.org" <jpoimboe@...nel.org>, "dave.hansen@...ux.intel.com"
	<dave.hansen@...ux.intel.com>, "daniel.sneddon@...ux.intel.com"
	<daniel.sneddon@...ux.intel.com>, "Lendacky, Thomas"
	<Thomas.Lendacky@....com>, "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
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	"mingo@...hat.com" <mingo@...hat.com>, "seanjc@...gle.com"
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	"pawan.kumar.gupta@...ux.intel.com" <pawan.kumar.gupta@...ux.intel.com>,
	"Moger, Babu" <Babu.Moger@....com>, "Das1, Sandipan" <Sandipan.Das@....com>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>, "hpa@...or.com"
	<hpa@...or.com>, "peterz@...radead.org" <peterz@...radead.org>,
	"bp@...en8.de" <bp@...en8.de>, "Kaplan, David" <David.Kaplan@....com>,
	"tglx@...utronix.de" <tglx@...utronix.de>, "x86@...nel.org" <x86@...nel.org>
Subject: Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature

On Mon, 2024-11-04 at 14:52 +0000, Andrew Cooper wrote:
> > Unfortunately, that's all we have right now in the official
> > documentation.
> > 
> > I've put up some notes in
> > https://amitshah.net/2024/11/eraps-reduces-software-tax-for-hardware-bugs/
> 
> I appreciate the attempt to get a few details out, but this is very
> confused on bunch of details.
> 
> Most importantly, you've described Intel RSB underflows, but named it
> AMD BTC.
> 
> "Retbleed" is two totally different things.   I begged the
> discoverers
> to give it two names, and I also begged the x86 maintainers to not
> alias
> them in Linux's view of the world, but alas.
> 
> AMD's BTC comes from a bad branch type prediction, and a late resteer
> from the ret uop executing.   It has nothing to do with RAS/RSB
> underflow conditions.

BTC indeed is only branch-type confusion.  The point I wanted to make
there is that to entirely get rid of X86_FEATURE_RSB_CTXW, I had to
confirm that AMD CPUs do not speculate return addresses from the BTB or
BHB since BTC was fixed.  (Or, in other words, to clarify the previous
comments there that said that AMD predicts from the BTB/BHB in every
case).

So - the only point in saying BTC_NO is relevant here is me confirming
that AMD is not going to speculate return addresses from outside of the
RSB. And that comment can now reflect reality.

		Amit

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