linux-kernel - Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature

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Message-ID: <bb90dce4-8963-476a-900b-40c3c00d8aac@intel.com>
Date: Mon, 4 Nov 2024 08:11:08 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: "Shah, Amit" <Amit.Shah@....com>,
 "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
 "x86@...nel.org" <x86@...nel.org>
Cc: "corbet@....net" <corbet@....net>,
 "boris.ostrovsky@...cle.com" <boris.ostrovsky@...cle.com>,
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 "pawan.kumar.gupta@...ux.intel.com" <pawan.kumar.gupta@...ux.intel.com>,
 "jpoimboe@...nel.org" <jpoimboe@...nel.org>,
 "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
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 <peterz@...radead.org>, "bp@...en8.de" <bp@...en8.de>,
 "Kaplan, David" <David.Kaplan@....com>
Subject: Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature

On 11/4/24 00:58, Shah, Amit wrote:
> Right - thanks, I'll have to reword that to say the RSB is flushed
> along with the TLB - so any action that causes the TLB to be flushed
> will also cause the RSB to be flushed.

Hold on though.

Is there a need for the RSB to be flushed at context switch?  You talked
about it like there was a need:

> any hardware TLB flush results in flushing of the RSB (aka RAP in
> AMD spec). This guarantees an RSB flush across context switches.