linux-kernel - Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature

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Message-ID: <b79c02aab50080cc8bee132eb5a0b12c42c4be06.camel@amd.com>
Date: Mon, 4 Nov 2024 16:13:18 +0000
From: "Shah, Amit" <Amit.Shah@....com>
To: "kvm@...r.kernel.org" <kvm@...r.kernel.org>, "dave.hansen@...el.com"
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Subject: Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature

On Mon, 2024-11-04 at 08:11 -0800, Dave Hansen wrote:
> On 11/4/24 00:58, Shah, Amit wrote:
> > Right - thanks, I'll have to reword that to say the RSB is flushed
> > along with the TLB - so any action that causes the TLB to be
> > flushed
> > will also cause the RSB to be flushed.
> 
> Hold on though.
> 
> Is there a need for the RSB to be flushed at context switch?  You
> talked
> about it like there was a need:
> 
> > any hardware TLB flush results in flushing of the RSB (aka RAP in
> > AMD spec). This guarantees an RSB flush across context switches.

I want to justify that not setting X86_FEATURE_RSB_CTXSW is still doing
the right thing, albeit in hardware.