Message-ID: <ab67af25-5a8f-42fd-8678-e4a1ede92f2c@oss.nxp.com>
Date: Mon, 4 Nov 2024 10:24:35 +0200
From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
To: Frank Li <Frank.li@....com>
Cc: Alexandre Belloni <alexandre.belloni@...tlin.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Catalin Marinas
 <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
 linux-rtc@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 NXP S32 Linux Team <s32@....com>, Christophe Lizzi <clizzi@...hat.com>,
 Alberto Ruiz <aruizrui@...hat.com>, Enric Balletbo <eballetb@...hat.com>,
 Bogdan Hamciuc <bogdan.hamciuc@....com>,
 Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>,
 IMX Review List <imx@...ts.linux.dev>
Subject: Re: [PATCH v3 2/4] rtc: s32g: add NXP S32G2/S32G3 SoC support

On 11/1/2024 7:55 PM, Frank Li wrote:
> On Fri, Nov 01, 2024 at 11:31:11AM +0200, Ciprian Marian Costea wrote:
>> On 10/31/2024 6:52 PM, Frank Li wrote:
>>> On Thu, Oct 31, 2024 at 10:35:55AM +0200, Ciprian Costea wrote:
>>>> From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
>>>>
> ...
> 
>>>
>>> why rtc is the clock provider?
>>>
>>
>> RTC clocking on S32G2/S32G3 has a clock mux for selecting between up to 4
>> different clock sources (parents).
>> By using this CCF framework I am selecting a specific clock source (parent).
> 
> If clock-mux is outside RTC block, it should be seperated clk provider
> driver.
> 
> If clock-mux is inside RTC block, it there are some input clk1, clk2,..clk4
> It should be handled by driver,
> 
> you can provide one of clk1..clk4 in dts, the driver check which one is not
> NULL, the set related mux register.
> 
> DT tree should not descript inside of RTC, just interface with outside
> parts.
> 
> Frank
> 

Hello Frank,

Thanks for your proposal. The clock mux is indeed inside the RTC block, 
as I've mentioned in previous replies [1].
Your proposal is IMHO similar to the version of this driver proposed in 
V0 [2] considering that from the 4 available RTC clock mux sources only 
2 are actually selectable by default on S32G (one is reserved and one 
relies on an external clock source).

Now, while your proposal is less complex and makes sense please consider 
that I am switching between clock mux sources in Runtime and Suspend 
states using 'assigned-*' CCF framework. I've already explained this 
clock mux switch [3] but on short the more precise RTC clock mux source 
is not been kept alive by hardware during Suspend, hence the need for 
switch to a different RTC clock source (since RTC is used as a wakeup 
source on S32G SoCs).
Related to your proposal, in V0 of this patchset, more information was 
added in the bindings in order to implement this clock switch (e.g 
'nxp,clksel') which was not accepted.

I hope this adds more context to the implementation proposal.

[1] 
https://lore.kernel.org/all/2815dcf8-bb90-4e3f-837d-2c2a36a8744e@oss.nxp.com/
[2] 
https://lore.kernel.org/all/20240911070028.127659-3-ciprianmarian.costea@oss.nxp.com/
[3] 
https://lore.kernel.org/all/2815dcf8-bb90-4e3f-837d-2c2a36a8744e@oss.nxp.com/

Ciprian

>>
>>>
>>>> +
>>>> +	if (priv->runtime_src_idx < 0) {
>>>> +		ret = priv->runtime_src_idx;
>>>> +		dev_err(dev, "RTC runtime clock source is not specified\n");
>>>> +		goto disable_ipg_clk;
>>>> +	}
>>>> +
>>>> +	ret = rtc_clk_src_switch(&priv->clk, priv->runtime_src_idx);
>>>> +	if (ret) {
>>>> +		dev_err(dev, "Failed clk source switch, err: %d\n", ret);
>>>> +		goto disable_ipg_clk;
>>>> +	}
>>>> +
>>>> +	platform_set_drvdata(pdev, priv);
>>>> +	priv->rdev->ops = &rtc_ops;
>>>> +
>>>> +	ret = devm_rtc_register_device(priv->rdev);
>>>> +	if (ret) {
>>>> +		dev_err(dev, "Failed to register RTC device\n");
>>>> +		goto disable_rtc;
>>>> +	}
>>>> +
>>>> +	ret = devm_request_irq(dev, priv->dt_irq_id,
>>>> +			       rtc_handler, 0, dev_name(dev), pdev);
>>>> +	if (ret) {
>>>> +		dev_err(dev, "Request interrupt %d failed, error: %d\n",
>>>> +			priv->dt_irq_id, ret);
>>>> +		goto disable_rtc;
>>>> +	}
>>>> +
>>>> +	return 0;
>>>> +
>>>> +disable_ipg_clk:
>>>> +	clk_disable_unprepare(priv->ipg);
>>>> +disable_rtc:
>>>> +	s32g_rtc_disable(priv);
>>>> +	return ret;
>>>> +}
>>>> +
>>>> +static void rtc_remove(struct platform_device *pdev)
>>>> +{
>>>> +	struct rtc_priv *priv = platform_get_drvdata(pdev);
>>>> +
>>>> +	s32g_rtc_disable(priv);
>>>> +}
>>>> +
>>>> +static void  __maybe_unused enable_api_irq(struct device *dev, unsigned int enabled)
>>>> +{
>>>> +	struct rtc_priv *priv = dev_get_drvdata(dev);
>>>> +	u32 api_irq = RTCC_APIEN | RTCC_APIIE;
>>>> +	u32 rtcc;
>>>> +
>>>> +	rtcc = ioread32(priv->rtc_base + RTCC_OFFSET);
>>>> +	if (enabled)
>>>> +		rtcc |= api_irq;
>>>> +	else
>>>> +		rtcc &= ~api_irq;
>>>> +	iowrite32(rtcc, priv->rtc_base + RTCC_OFFSET);
>>>> +}
>>>> +
>>>> +static int __maybe_unused rtc_suspend(struct device *dev)
>>>> +{
>>>> +	struct rtc_priv *init_priv = dev_get_drvdata(dev);
>>>> +	struct rtc_priv priv;
>>>> +	long long base_sec;
>>>> +	int ret = 0;
>>>> +	u32 rtcval;
>>>> +	u32 sec;
>>>> +
>>>> +	if (!device_may_wakeup(dev))
>>>> +		return 0;
>>>> +
>>>> +	if (init_priv->suspend_src_idx < 0)
>>>> +		return 0;
>>>> +
>>>> +	if (rtc_clk_get_parent(&init_priv->clk) == init_priv->suspend_src_idx)
>>>> +		return 0;
>>>> +
>>>> +	/* Save last known timestamp before we switch clocks and reinit RTC */
>>>> +	ret = s32g_rtc_read_time(dev, &init_priv->base.tm);
>>>> +	if (ret)
>>>> +		return ret;
>>>> +
>>>> +	/*
>>>> +	 * Use a local copy of the RTC control block to
>>>> +	 * avoid restoring it on resume path.
>>>> +	 */
>>>> +	memcpy(&priv, init_priv, sizeof(priv));
>>>> +
>>>> +	ret = get_time_left(dev, init_priv, &sec);
>>>> +	if (ret)
>>>> +		return ret;
>>>> +
>>>> +	/* Adjust for the number of seconds we'll be asleep */
>>>> +	base_sec = rtc_tm_to_time64(&init_priv->base.tm);
>>>> +	base_sec += sec;
>>>> +	rtc_time64_to_tm(base_sec, &init_priv->base.tm);
>>>> +
>>>> +	ret = rtc_clk_src_switch(&priv.clk, priv.suspend_src_idx);
>>>> +	if (ret) {
>>>> +		dev_err(dev, "Failed clk source switch, err: %d\n", ret);
>>>> +		return ret;
>>>> +	}
>>>> +
>>>> +	ret = sec_to_rtcval(&priv, sec, &rtcval);
>>>> +	if (ret) {
>>>> +		dev_warn(dev, "Alarm is too far in the future\n");
>>>> +		return ret;
>>>> +	}
>>>> +
>>>> +	s32g_rtc_alarm_irq_enable(dev, 0);
>>>> +	enable_api_irq(dev, 1);
>>>> +	iowrite32(rtcval, priv.rtc_base + APIVAL_OFFSET);
>>>> +	iowrite32(0, priv.rtc_base + RTCVAL_OFFSET);
>>>> +
>>>> +	return ret;
>>>> +}
>>>> +
>>>> +static int __maybe_unused rtc_resume(struct device *dev)
>>>> +{
>>>> +	struct rtc_priv *priv = dev_get_drvdata(dev);
>>>> +	int ret;
>>>> +
>>>> +	if (!device_may_wakeup(dev))
>>>> +		return 0;
>>>> +
>>>> +	if (rtc_clk_get_parent(&priv->clk) == priv->runtime_src_idx)
>>>> +		return 0;
>>>> +
>>>> +	/* Disable wake-up interrupts */
>>>> +	enable_api_irq(dev, 0);
>>>> +
>>>> +	ret = rtc_clk_src_switch(&priv->clk, priv->runtime_src_idx);
>>>> +	if (ret) {
>>>> +		dev_err(dev, "Failed clk source switch, err: %d\n", ret);
>>>> +		return ret;
>>>> +	}
>>>> +
>>>> +	/*
>>>> +	 * Now RTCCNT has just been reset, and is out of sync with priv->base;
>>>> +	 * reapply the saved time settings
>>>> +	 */
>>>> +	return s32g_rtc_set_time(dev, &priv->base.tm);
>>>> +}
>>>> +
>>>> +static const struct of_device_id rtc_dt_ids[] = {
>>>> +	{ .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data},
>>>> +	{ /* sentinel */ },
>>>> +};
>>>> +
>>>> +static SIMPLE_DEV_PM_OPS(rtc_pm_ops,
>>>> +			 rtc_suspend, rtc_resume);
>>>> +
>>>> +static struct platform_driver rtc_driver = {
>>>> +	.driver		= {
>>>> +		.name			= "s32g-rtc",
>>>> +		.pm				= &rtc_pm_ops,
>>>> +		.of_match_table = rtc_dt_ids,
>>>> +	},
>>>> +	.probe		= rtc_probe,
>>>> +	.remove	= rtc_remove,
>>>> +};
>>>> +module_platform_driver(rtc_driver);
>>>> +
>>>> +MODULE_AUTHOR("NXP");
>>>> +MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3");
>>>> +MODULE_LICENSE("GPL");
>>>> --
>>>> 2.45.2
>>>>
>>

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