linux-kernel - Re: [PATCH v5 3/7] arm64: dts: s32g: make pinctrl part of mfd node

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Message-ID: <88fd2cba-081d-48e9-8733-4cb6eecaac9f@oss.nxp.com>
Date: Mon, 4 Nov 2024 13:33:35 +0200
From: Andrei Stefanescu <andrei.stefanescu@....nxp.com>
To: Frank Li <Frank.li@....com>
Cc: Linus Walleij <linus.walleij@...aro.org>,
 Bartosz Golaszewski <brgl@...ev.pl>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Chester Lin <chester62515@...il.com>,
 Matthias Brugger <mbrugger@...e.com>,
 Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>,
 Larisa Grigore <larisa.grigore@....com>,
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 "Rafael J. Wysocki" <rafael@...nel.org>, Lee Jones <lee@...nel.org>,
 Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
 Fabio Estevam <festevam@...il.com>, Dong Aisheng <aisheng.dong@....com>,
 Jacky Bai <ping.bai@....com>, linux-gpio@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, NXP S32 Linux Team <s32@....com>,
 Christophe Lizzi <clizzi@...hat.com>, Alberto Ruiz <aruizrui@...hat.com>,
 Enric Balletbo <eballetb@...hat.com>,
 Pengutronix Kernel Team <kernel@...gutronix.de>, imx@...ts.linux.dev
Subject: Re: [PATCH v5 3/7] arm64: dts: s32g: make pinctrl part of mfd node

Hi Frank,

On 01/11/2024 20:22, Frank Li wrote:
> On Fri, Nov 01, 2024 at 10:06:09AM +0200, Andrei Stefanescu wrote:
>> SIUL2 is now represented as an mfd device. Therefore, the old
>> pinctrl node is deprecated. Move the pinctrl related properties
>> inside the new "nxp-siul2" node. The latter one is now used
>> to represent the mfd device.
> 
> Generally, dt team want you to keep both for sometime to keep
> back compatiblity.

Just to make sure I understand correctly, I will keep the previous pinctrl
node and have both the new siul2 node and the old pinctrl one, right?

Best regards,
Andrei

> 
> Frank
>>
>> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@....nxp.com>
>> ---
>>  arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++-------------
>>  arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++-------------
>>  2 files changed, 24 insertions(+), 28 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> index fa054bfe7d5c..e14ce5503e1f 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>> @@ -114,20 +114,18 @@ soc@0 {
>>  		#size-cells = <1>;
>>  		ranges = <0 0 0 0x80000000>;
>>
>> -		pinctrl: pinctrl@...9c240 {
>> -			compatible = "nxp,s32g2-siul2-pinctrl";
>> -				/* MSCR0-MSCR101 registers on siul2_0 */
>> -			reg = <0x4009c240 0x198>,
>> -				/* MSCR112-MSCR122 registers on siul2_1 */
>> -			      <0x44010400 0x2c>,
>> -				/* MSCR144-MSCR190 registers on siul2_1 */
>> -			      <0x44010480 0xbc>,
>> -				/* IMCR0-IMCR83 registers on siul2_0 */
>> -			      <0x4009ca40 0x150>,
>> -				/* IMCR119-IMCR397 registers on siul2_1 */
>> -			      <0x44010c1c 0x45c>,
>> -				/* IMCR430-IMCR495 registers on siul2_1 */
>> -			      <0x440110f8 0x108>;
>> +		siul2: siul2@...9c000 {
>> +			compatible = "nxp,s32g2-siul2";
>> +			reg = <0x4009c000 0x179c>,
>> +			      <0x44010000 0x17b0>;
>> +			reg-names = "siul20", "siul21";
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>;
>> +			gpio-reserved-ranges = <102 10>, <123 21>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
>>
>>  			jtag_pins: jtag-pins {
>>  				jtag-grp0 {
>> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> index b4226a9143c8..fa43d036686f 100644
>> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
>> @@ -171,20 +171,18 @@ soc@0 {
>>  		#size-cells = <1>;
>>  		ranges = <0 0 0 0x80000000>;
>>
>> -		pinctrl: pinctrl@...9c240 {
>> -			compatible = "nxp,s32g2-siul2-pinctrl";
>> -				/* MSCR0-MSCR101 registers on siul2_0 */
>> -			reg = <0x4009c240 0x198>,
>> -				/* MSCR112-MSCR122 registers on siul2_1 */
>> -			      <0x44010400 0x2c>,
>> -				/* MSCR144-MSCR190 registers on siul2_1 */
>> -			      <0x44010480 0xbc>,
>> -				/* IMCR0-IMCR83 registers on siul2_0 */
>> -			      <0x4009ca40 0x150>,
>> -				/* IMCR119-IMCR397 registers on siul2_1 */
>> -			      <0x44010c1c 0x45c>,
>> -				/* IMCR430-IMCR495 registers on siul2_1 */
>> -			      <0x440110f8 0x108>;
>> +		siul2: siul2@...9c000 {
>> +			compatible = "nxp,s32g3-siul2";
>> +			reg = <0x4009c000 0x179c>,
>> +			      <0x44010000 0x17b0>;
>> +			reg-names = "siul20", "siul21";
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>;
>> +			gpio-reserved-ranges = <102 10>, <123 21>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
>>
>>  			jtag_pins: jtag-pins {
>>  				jtag-grp0 {
>> --
>> 2.45.2
>>