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Message-ID: <20241104132221.GB2504924@rocinante>
Date: Mon, 4 Nov 2024 22:22:21 +0900
From: Krzysztof WilczyƄski <kw@...ux.com>
To: Siddharth Vadapalli <s-vadapalli@...com>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, robh@...nel.org,
	vigneshr@...com, manivannan.sadhasivam@...aro.org,
	kishon@...nel.org, thomas.richard@...tlin.com,
	linux-omap@...r.kernel.org, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	srk@...com
Subject: Re: [PATCH v2] PCI: j721e: Deassert PERST# after a delay of
 PCIE_T_PVPERL_MS ms

Hello,

> According to Section 2.2 of the PCI Express Card Electromechanical
> Specification (Revision 5.1), in order to ensure that the power and the
> reference clock are stable, PERST# has to be deasserted after a delay of
> 100 milliseconds (TPVPERL). Currently, it is being assumed that the power
> is already stable, which is not necessarily true. Hence, change the delay
> to PCIE_T_PVPERL_MS to guarantee that power and reference clock are stable.

Applied to controller/j721e, thank you!

[01/01] PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds
        https://git.kernel.org/pci/pci/c/22a9120479a4

	Krzysztof

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