linux-kernel - Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

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Message-ID: <lkxm6m2u25o4qfvpja7qsldqm7zjxejkn6d5qihyxbg2zvntwh@icvun74e6rll>
Date: Thu, 7 Nov 2024 16:34:36 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Linus Walleij <linus.walleij@...aro.org>
Cc: Sudeep Holla <sudeep.holla@....com>, Ard Biesheuvel <ardb@...nel.org>, 
	Russell King <linux@...linux.org.uk>, linux-arm-kernel@...ts.infradead.org, 
	linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, 
	Arnd Bergmann <arnd@...db.de>
Subject: Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

On Thu, Nov 07, 2024 at 02:55:55PM +0100, Linus Walleij wrote:
> Hi Dmitry,
> 
> On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov
> <dmitry.baryshkov@...aro.org> wrote:
> 
> > Follow the ARM64 platform and implement simple cache information driver.
> > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> > limited to the ARMv7 / ARMv7M, providing simple fallback or just
> > returning -EOPNOTSUPP in case of older platforms.
> >
> > In theory we should be able to skip CLIDR reading and assume that Dcache
> > and Icache (or unified L1 cache) always exist if CTR is supported and
> > returns sensible value. However I think this better be handled by the
> > maintainers of corresponding platforms.
> >
> > Other than just providing information to the userspace, this patchset is
> > required in order to implement L2 cache driver (and in the end CPU
> > frequency scaling) on ARMv7-based Qualcomm devices.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> 
> I added my review tags to the v2 patches, can you put them
> into Russell's patch tracker?

Done, 9432/1 and 9433/1, thank you!

-- 
With best wishes
Dmitry