linux-kernel - Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

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Message-ID: <CACRpkdbfckBBW5W5sEvz1LwzdOvTKi_fi7tDu+9nPeKumYkPeA@mail.gmail.com>
Date: Thu, 7 Nov 2024 14:55:55 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Sudeep Holla <sudeep.holla@....com>, Ard Biesheuvel <ardb@...nel.org>, 
	Russell King <linux@...linux.org.uk>, linux-arm-kernel@...ts.infradead.org, 
	linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, 
	Arnd Bergmann <arnd@...db.de>
Subject: Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

Hi Dmitry,

On Mon, Oct 14, 2024 at 3:55 PM Dmitry Baryshkov
<dmitry.baryshkov@...aro.org> wrote:

> Follow the ARM64 platform and implement simple cache information driver.
> As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> limited to the ARMv7 / ARMv7M, providing simple fallback or just
> returning -EOPNOTSUPP in case of older platforms.
>
> In theory we should be able to skip CLIDR reading and assume that Dcache
> and Icache (or unified L1 cache) always exist if CTR is supported and
> returns sensible value. However I think this better be handled by the
> maintainers of corresponding platforms.
>
> Other than just providing information to the userspace, this patchset is
> required in order to implement L2 cache driver (and in the end CPU
> frequency scaling) on ARMv7-based Qualcomm devices.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

I added my review tags to the v2 patches, can you put them
into Russell's patch tracker?

Yours,
Linus Walleij