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Message-ID: <Zy3iogT7jOLEvf1S@pengfei-OptiPlex-Tower-Plus-7010>
Date: Fri, 8 Nov 2024 18:06:26 +0800
From: Pengfei Li <pengfei.li_1@....com>
To: Alexander Stein <alexander.stein@...tq-group.com>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
festevam@...il.com, linux-arm-kernel@...ts.infradead.org,
joao.goncalves@...adex.com, frieder.schrempf@...tron.de,
marex@...x.de, hvilleneuve@...onoff.com, peng.fan@....com,
m.othacehe@...il.com, mwalle@...nel.org,
Max.Merchel@...tq-group.com, hiago.franco@...adex.com,
tharvey@...eworks.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, imx@...ts.linux.dev, ping.bai@....com,
ye.li@....com, aisheng.dong@....com, frank.li@....com
Subject: Re: [PATCH 2/3] arm64: dts: freescale: Add i.MX91 dtsi support
On Thu, Nov 07, 2024 at 02:06:27PM +0100, Alexander Stein wrote:
> Am Donnerstag, 7. November 2024, 13:49:50 CET schrieb Alexander Stein:
> > > diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi
> > > new file mode 100644
> > > index 000000000000..a9f4c1fe61cc
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi
> > > @@ -0,0 +1,66 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright 2024 NXP
> > > + */
> > > +
> > > +#include "imx91-pinfunc.h"
> > > +#include "imx93.dtsi"
> > > +
> > > +&{/thermal-zones/cpu-thermal/cooling-maps/map0} {
> > > + cooling-device =
> > > + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > > +};
> > > +
> > > +&clk {
> > > + compatible = "fsl,imx91-ccm";
> > > +};
> > > +
> > > +&eqos {
> > > + clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
> > > + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
> > > + <&clk IMX91_CLK_ENET_TIMER>,
> > > + <&clk IMX91_CLK_ENET1_QOS_TSN>,
> > > + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
> > > + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
> > > + <&clk IMX91_CLK_ENET1_QOS_TSN>;
> > > + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> > > + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
> >
> > Is it just me or is the alignment of new lines not matching?
> >
> >
> > > +};
> > > +
> > > +&fec {
> > > + clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
> > > + <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
> > > + <&clk IMX91_CLK_ENET_TIMER>,
> > > + <&clk IMX91_CLK_ENET2_REGULAR>,
> > > + <&clk IMX93_CLK_DUMMY>;
> > > + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
> > > + <&clk IMX91_CLK_ENET2_REGULAR>;
> > > + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> > > + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
> >
> > Here as well: Is it just me or is the alignment of new lines not matching?
> >
> > > + assigned-clock-rates = <100000000>, <250000000>;
> > > +};
> > > +
> > > +&i3c1 {
> > > + clocks = <&clk IMX93_CLK_BUS_AON>,
> > > + <&clk IMX93_CLK_I3C1_GATE>,
> > > + <&clk IMX93_CLK_DUMMY>;
> > > +};
> > > +
> > > +&i3c2 {
> > > + clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
> > > + <&clk IMX93_CLK_I3C2_GATE>,
> > > + <&clk IMX93_CLK_DUMMY>;
> > > +};
> > > +
> > > +&tmu {
> > > + status = "disabled";
> >
> > Why does the TMU needs to be disabled instead of deleted?
> >
> > > +};
> > > +
> > > +/* i.MX91 only has one A core */
> > > +/delete-node/ &A55_1;
> > > +
> > > +/* i.MX91 not has cm33 */
> > > +/delete-node/ &cm33;
> > > +
> > > +/* i.MX91 not has power-domain@...61800 */
> > > +/delete-node/ &mlmix;
> > >
> >
> > Shouldn't the following node also be removed?
> > * mipi_csi
> > * dsi
> > * lvds_bridge
> > * lcdif_to_dsi
> > * lcdif_to_ldb
>
> Add mu1 and mu2 to that list.
Hi, i.MX91 also has mu1 and mu2. so there is no need to remove them here.
BR,
Pengfei Li
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