| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20241112-sa8775p-cpufreq-l3-ddr-scaling-v2-1-53d256b3f2a7@quicinc.com>
Date: Tue, 12 Nov 2024 18:14:11 +0530
From: Jagadeesh Kona <quic_jkona@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
CC: Ajit Pandey <quic_ajipan@...cinc.com>,
Imran Shaik
<quic_imrashai@...cinc.com>,
Taniya Das <quic_tdas@...cinc.com>,
"Satya Priya
Kakitapalli" <quic_skakitap@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Jagadeesh Kona
<quic_jkona@...cinc.com>,
Shivnandan Kumar <quic_kshivnan@...cinc.com>
Subject: [PATCH v2 1/2] arm64: dts: qcom: sa8775p: Add CPU OPP tables to
scale DDR/L3
Add OPP tables required to scale DDR and L3 per freq-domain
on SA8775P platform.
Co-developed-by: Shivnandan Kumar <quic_kshivnan@...cinc.com>
Signed-off-by: Shivnandan Kumar <quic_kshivnan@...cinc.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 211 ++++++++++++++++++++++++++++++++++
1 file changed, 211 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index e790d74de96278389082fc3670765b383fab1e70..1d2b45bde03fa28b47639ce4f4d7c38e352d84de 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
@@ -49,6 +50,11 @@ cpu0: cpu@0 {
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -71,6 +77,11 @@ cpu1: cpu@100 {
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -88,6 +99,11 @@ cpu2: cpu@200 {
next-level-cache = <&l2_2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -105,6 +121,11 @@ cpu3: cpu@300 {
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -122,6 +143,11 @@ cpu4: cpu@...00 {
next-level-cache = <&l2_4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -145,6 +171,11 @@ cpu5: cpu@...00 {
next-level-cache = <&l2_5>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -162,6 +193,11 @@ cpu6: cpu@...00 {
next-level-cache = <&l2_6>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -179,6 +215,11 @@ cpu7: cpu@...00 {
next-level-cache = <&l2_7>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
l2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -268,6 +309,176 @@ cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
};
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_opp_1267mhz: opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <6220800 29491200>;
+ };
+
+ cpu0_opp_1363mhz: opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <6220800 29491200>;
+ };
+
+ cpu0_opp_1459mhz: opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <6220800 29491200>;
+ };
+
+ cpu0_opp_1536mhz: opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <6220800 29491200>;
+ };
+
+ cpu0_opp_1632mhz: opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu0_opp_1708mhz: opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu0_opp_1785mhz: opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu0_opp_1862mhz: opp-1862400000 {
+ opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu0_opp_1939mhz: opp-1939200000 {
+ opp-hz = /bits/ 64 <1939200000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu0_opp_2016mhz: opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu0_opp_2112mhz: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <8371200 49766400>;
+ };
+
+ cpu0_opp_2188mhz: opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <8371200 49766400>;
+ };
+
+ cpu0_opp_2265mhz: opp-2265600000 {
+ opp-hz = /bits/ 64 <2265600000>;
+ opp-peak-kBps = <8371200 49766400>;
+ };
+
+ cpu0_opp_2361mhz: opp-2361600000 {
+ opp-hz = /bits/ 64 <2361600000>;
+ opp-peak-kBps = <12787200 51609600>;
+ };
+
+ cpu0_opp_2457mhz: opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <12787200 51609600>;
+ };
+
+ cpu0_opp_2553mhz: opp-2553600000 {
+ opp-hz = /bits/ 64 <2553600000>;
+ opp-peak-kBps = <12787200 54681600>;
+ };
+ };
+
+ cpu4_opp_table: opp-table-cpu4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu4_opp_1267mhz: opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <6220800 29491200>;
+ };
+
+ cpu4_opp_1363mhz: opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <6220800 29491200>;
+ };
+
+ cpu4_opp_1459mhz: opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <6220800 29491200>;
+ };
+
+ cpu4_opp_1536mhz: opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <6220800 29491200>;
+ };
+
+ cpu4_opp_1632mhz: opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu4_opp_1708mhz: opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu4_opp_1785mhz: opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu4_opp_1862mhz: opp-1862400000 {
+ opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu4_opp_1939mhz: opp-1939200000 {
+ opp-hz = /bits/ 64 <1939200000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu4_opp_2016mhz: opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <6835200 39321600>;
+ };
+
+ cpu4_opp_2112mhz: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <8371200 49766400>;
+ };
+
+ cpu4_opp_2188mhz: opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <8371200 49766400>;
+ };
+
+ cpu4_opp_2265mhz: opp-2265600000 {
+ opp-hz = /bits/ 64 <2265600000>;
+ opp-peak-kBps = <8371200 49766400>;
+ };
+
+ cpu4_opp_2361mhz: opp-2361600000 {
+ opp-hz = /bits/ 64 <2361600000>;
+ opp-peak-kBps = <12787200 51609600>;
+ };
+
+ cpu4_opp_2457mhz: opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <12787200 51609600>;
+ };
+
+ cpu4_opp_2553mhz: opp-2553600000 {
+ opp-hz = /bits/ 64 <2553600000>;
+ opp-peak-kBps = <12787200 54681600>;
+ };
+ };
+
dummy-sink {
compatible = "arm,coresight-dummy-sink";
--
2.34.1
Powered by blists - more mailing lists