linux-kernel - Re: [PATCH v1 3/5] ARM: dts: aspeed: Harma: Revise GPIO line name

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Message-ID: <CAPSyxFRC-VBVs4xBFnkoBNx1jNjr+cJ_CztmgCpMzqtjYDCVbg@mail.gmail.com>
Date: Tue, 12 Nov 2024 17:45:49 +0800
From: Peter Yin <peteryin.openbmc@...il.com>
To: Andrew Jeffery <andrew@...econstruct.com.au>
Cc: Rob Herring <robh+dt@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, 
	Joel Stanley <joel@....id.au>, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-aspeed@...ts.ozlabs.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 3/5] ARM: dts: aspeed: Harma: Revise GPIO line name

On Tue, Nov 12, 2024 at 7:53 AM Andrew Jeffery
<andrew@...econstruct.com.au> wrote:
>
> Hi Peter,
>
> On Mon, 2024-11-11 at 17:43 +0800, Peter Yin wrote:
> >   Add:
> >     "ac-power-button",
> >     "asic0-card-type-detection0-n"
> >     "asic0-card-type-detection1-n"
> >     "asic0-card-type-detection2-n"
> >
> >     "cpu0-prochot-alert",
> >     "cpu0-thermtrip-alert",
> >
> >     "irq-uv-detect-alert",
> >     "irq-hsc-alert",
> >
> >     "uart-switch-button"
> >     "uart-switch-lsb"
> >     "uart-switch-msb"
> >
> >     "leakage-detect-alert",
> >
> >     "power-card-enable",
> >     "power-fault-n",
> >     "power-hsc-good",
> >     "power-chassis-good"
> >     "presence-post-card",
> >     "presence-cmm"
> >     "pvdd11-ocp-alert"
> >
> >     "reset-control-cmos-clear"
> >     "reset-cause-pcie",
> >     "reset-cause-platrst",
> >
> >     "P0_I3C_APML_ALERT_L",
>
> Rather than list the identifiers that are already contained in the
> patch, can you please discuss what functionality these identifiers
> enable, how different functions are related, and why this must all be
> done in one patch?
>
> >
> >   Rename:
> >     "power-cpu-good" to "host0-ready",
> >     "host-ready-n" to "post-end-n
>
> On the other-hand, explicitly calling out these changes is helpful, but
> please also discuss the motivation and impact.
>
> Andrew

Hi Andrew,
    Understood, I'll include comments in the next version. Harma will
be moving into the DVT2 stage,
and many of the new GPIO lines weren't defined in the POC stage, so
I'll add this to the one page.

Thanks,
Peter.