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Message-ID: <dbdb45ed1135e73b4eebd76e6f61b96d48aaedc6.camel@mediatek.com>
Date: Tue, 12 Nov 2024 10:08:31 +0000
From: SkyLake Huang (黃啟澤)
<SkyLake.Huang@...iatek.com>
To: "dev@...herer.org" <dev@...herer.org>, "d-gole@...com" <d-gole@...com>,
"vigneshr@...com" <vigneshr@...com>, "miquel.raynal@...tlin.com"
<miquel.raynal@...tlin.com>, "gch981213@...il.com" <gch981213@...il.com>,
"mmkurbanov@...utedevices.com" <mmkurbanov@...utedevices.com>,
"richard@....at" <richard@....at>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
"kernel@...rdevices.ru" <kernel@...rdevices.ru>
Subject: Re: [PATCH v2] mtd: spinand: add support for FORESEE F35SQA002G
Hi Miquel/Martin,
About this driver, including F35SQA001G/F35SQA002G parts, I'm concerned
that the driver will always use 32H for update_cache operations, which
means it's not compitable with those SPI controller who can't transmit
2048 bytes (most small-density SPI-NAND's page size nowadays) at one
time.
The following controller's driver seems that they can't transmit 2048
bytes in one transmission:
- spi-amd.c: 64 bytes (AMD_SPI_MAX_DATA)
- spi-amlogic-spifc-a1.c: 512 bytes (SPIFC_A1_BUFFER_SIZE)
- spi-fsl-qspi.c: 1KB
- spi-hisi-sfc-v3xx.c: 64*6 bytes
- spi-intel.c: 64 bytes (INTEL_SPI_FIFO_SZ)
- spi-microchip-core-qspi.c: 256 bytesc (MAX_DATA_CMD_LEN)
- spi-nxp-fspi.c: TX:1KB, RX: 512B in FIFO mode
- spi-wpcm-fiu.c: 4B
I guess we need to add some check to make sure that F35SQA series work
only with those SPI controllers who can transmit more than 2048
bytes(NAND page size) at one time?
BRs,
Sky
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