linux-kernel - Re: [PATCH v5 00/13] Zacas/Zabha support and qspinlocks

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Message-Id: 
 <173151077674.1250875.11061543352254749516.git-patchwork-notify@kernel.org>
Date: Wed, 13 Nov 2024 15:12:56 +0000
From: patchwork-bot+linux-riscv@...nel.org
To: Alexandre Ghiti <alexghiti@...osinc.com>
Cc: linux-riscv@...ts.infradead.org, corbet@....net, paul.walmsley@...ive.com,
 palmer@...belt.com, aou@...s.berkeley.edu, conor@...nel.org, robh@...nel.org,
 krzk+dt@...nel.org, parri.andrea@...il.com, nathan@...nel.org,
 peterz@...radead.org, mingo@...hat.com, will@...nel.org, longman@...hat.com,
 boqun.feng@...il.com, arnd@...db.de, leobras@...hat.com, guoren@...nel.org,
 linux-doc@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arch@...r.kernel.org
Subject: Re: [PATCH v5 00/13] Zacas/Zabha support and qspinlocks

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@...osinc.com>:

On Sun, 18 Aug 2024 08:35:25 +0200 you wrote:
> This implements [cmp]xchgXX() macros using Zacas and Zabha extensions
> and finally uses those newly introduced macros to add support for
> qspinlocks: note that this implementation of qspinlocks satisfies the
> forward progress guarantee.
> 
> It also uses Ziccrse to provide the qspinlock implementation.
> 
> [...]

Here is the summary with links:
  - [v5,01/13] riscv: Move cpufeature.h macros into their own header
    https://git.kernel.org/riscv/c/010e12aa4925
  - [v5,02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs
    https://git.kernel.org/riscv/c/af042c457db0
  - [v5,03/13] riscv: Implement cmpxchg32/64() using Zacas
    https://git.kernel.org/riscv/c/38acdee32d23
  - [v5,04/13] dt-bindings: riscv: Add Zabha ISA extension description
    (no matching commit)
  - [v5,05/13] riscv: Implement cmpxchg8/16() using Zabha
    (no matching commit)
  - [v5,06/13] riscv: Improve zacas fully-ordered cmpxchg()
    (no matching commit)
  - [v5,07/13] riscv: Implement arch_cmpxchg128() using Zacas
    https://git.kernel.org/riscv/c/f7bd2be7663c
  - [v5,08/13] riscv: Implement xchg8/16() using Zabha
    https://git.kernel.org/riscv/c/97ddab7fbea8
  - [v5,09/13] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock
    https://git.kernel.org/riscv/c/cbe82e140bb7
  - [v5,10/13] asm-generic: ticket-lock: Add separate ticket-lock.h
    https://git.kernel.org/riscv/c/22c33321e260
  - [v5,11/13] riscv: Add ISA extension parsing for Ziccrse
    (no matching commit)
  - [v5,12/13] dt-bindings: riscv: Add Ziccrse ISA extension description
    https://git.kernel.org/riscv/c/447b2afbcde1
  - [v5,13/13] riscv: Add qspinlock support
    (no matching commit)

You are awesome, thank you!
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