| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID:
<MA0P287MB2822642BE6F4B448410A28FAFE5B2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>
Date: Thu, 14 Nov 2024 10:51:23 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Rob Herring <robh@...nel.org>, Chen Wang <unicornxw@...il.com>
Cc: kw@...ux.com, u.kleine-koenig@...libre.com, aou@...s.berkeley.edu,
arnd@...db.de, bhelgaas@...gle.com, conor+dt@...nel.org, guoren@...nel.org,
inochiama@...look.com, krzk+dt@...nel.org, lee@...nel.org,
lpieralisi@...nel.org, manivannan.sadhasivam@...aro.org, palmer@...belt.com,
paul.walmsley@...ive.com, pbrobinson@...il.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
linux-riscv@...ts.infradead.org, chao.wei@...hgo.com,
xiaoguang.xing@...hgo.com, fengchun.li@...hgo.com
Subject: Re: [PATCH 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host
On 2024/11/12 23:59, Rob Herring wrote:
> On Mon, Nov 11, 2024 at 01:59:37PM +0800, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@...look.com>
>>
>> Add binding for Sophgo SG2042 PCIe host controller.
>>
>> Signed-off-by: Chen Wang <unicorn_wang@...look.com>
>> ---
>> .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 88 +++++++++++++++++++
>> 1 file changed, 88 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
>> new file mode 100644
>> index 000000000000..d4d2232f354f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
>> @@ -0,0 +1,88 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)
>> +
>> +description: |+
> Don't need '|+'
Got, thanks.
>
>> + Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.
>> + It shares common features with the PCIe core and inherits common properties
>> + defined in Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml.
> That's clear from the $ref. No need to say that in prose.
Got, thanks.
>
>> +
>> +maintainers:
>> + - Chen Wang <unicorn_wang@...look.com>
>> +
>> +properties:
>> + compatible:
>> + const: sophgo,sg2042-pcie-host
>> +
>> + reg:
>> + maxItems: 2
>> +
>> + reg-names:
>> + items:
>> + - const: reg
>> + - const: cfg
>> +
>> + sophgo,syscon-pcie-ctrl:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description: Phandle to the SYSCON entry
> Please describe what you need to access.
>
>> +
>> + sophgo,link-id:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: Cadence IP link ID.
> Is this an index or related to the syscon? Nak for the former, use
> linux,pci-domain. For the latter, add an arg to sophgo,syscon-pcie-ctrl.
Let me give you some background info.
SG2042 uses Cadence IP, every IP is composed of 2 cores(called link0 &
link1 as Cadence's term). The Cadence IP has two modes of operation,
selected by a strap pin.
In the single-link mode, the Cadence PCIe core instance associated with
Link0 is connected to all the lanes and the Cadence PCIe core instance
associated with Link1 is inactive.
In the dual-link mode, the Cadence PCIe core instance associated with
Link0 is connected to the lower half of the lanes and the Cadence PCIe
core instance associated with Link1 is connected to the upper half of
the lanes.
SG2042 contains 2 Cadence IPs and configures the Cores as below:
```
+-- Core(Link0) <---> pcie_rc0 +-----------------+
Cadence IP 1 --+ | cdns_pcie0_ctrl |
+-- Core(Link1) <---> disabled +-----------------+
+-- Core(Link0) <---> pcie_rc1 +-----------------+
Cadence IP 2 --+ | cdns_pcie1_ctrl |
+-- Core(Link1) <---> pcie_rc2 +-----------------+
```
pcie_rcX is pcie node ("sophgo,sg2042-pcie-host") defined in DTS.
cdns_pcie0_ctrl is syscon node ("sophgo,sg2042-pcie-ctrl") defined in DTS
cdns_pcieX_ctrl contains some registers shared by pcie_rcX, even two
RC(Link)s may share different bits of the same register. For
example，cdns_pcie1_ctrl contains registers shared by link0 & link1 for
Cadence IP 2.
So we defined "sophgo,link-id" to flag which core(link) the rc maps to,
with this we can know what registers(bits) we should use.
That's why I don't use "linux,pci-domain" and also it's not proper to
define it as arg to "sophgo,syscon-pcie-ctrl".
>> +
>> + sophgo,internal-msi:
>> + $ref: /schemas/types.yaml#/definitions/flag
>> + description: Identifies whether the PCIE node uses internal MSI controller.
> Wouldn't 'msi-parent' work for this purpose?
I will check it out, thanks.
>
>> +
>> + vendor-id:
>> + const: 0x1f1c
>> +
>> + device-id:
>> + const: 0x2042
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + interrupt-names:
>> + const: msi
>> +
>> +allOf:
>> + - $ref: cdns-pcie-host.yaml#
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - sophgo,syscon-pcie-ctrl
>> + - sophgo,link-id
>> + - vendor-id
>> + - device-id
>> + - ranges
> ranges is already required in the common schemas.
Got.
>> +
>> +additionalProperties: true
>> +
>> +examples:
>> + - |
>> + pcie@...00000 {
>> + compatible = "sophgo,sg2042-pcie-host";
>> + device_type = "pci";
>> + reg = <0x62000000 0x00800000>,
>> + <0x48000000 0x00001000>;
>> + reg-names = "reg", "cfg";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
>> + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
>> + bus-range = <0x80 0xbf>;
>> + vendor-id = <0x1f1c>;
>> + device-id = <0x2042>;
>> + cdns,no-bar-match-nbits = <48>;
>> + sophgo,link-id = <0>;
>> + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
>> + sophgo,internal-msi;
>> + interrupt-parent = <&intc>;
>> + };
>> --
>> 2.34.1
>>
Powered by blists - more mailing lists