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Message-ID: <0509452b-586b-4e06-b344-6f68af4593f0@oss.qualcomm.com>
Date: Thu, 14 Nov 2024 14:03:47 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Ziyue Zhang <quic_ziyuzhan@...cinc.com>, vkoul@...nel.org,
kishon@...nel.org, robh+dt@...nel.org,
manivannan.sadhasivam@...aro.org, bhelgaas@...gle.com, kw@...ux.com,
lpieralisi@...nel.org, quic_qianyu@...cinc.com, conor+dt@...nel.org,
neil.armstrong@...aro.org, andersson@...nel.org,
konradybcio@...nel.org
Cc: quic_shashim@...cinc.com, quic_kaushalk@...cinc.com, quic_tdas@...cinc.com,
quic_tingweiz@...cinc.com, quic_aiquny@...cinc.com, kernel@...cinc.com,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
Krishna chaitanya chundru <quic_krichai@...cinc.com>
Subject: Re: [PATCH 5/5] arm64: dts: qcom: qcs8300: enable pcie1 for QCS8300
On 14.11.2024 10:54 AM, Ziyue Zhang wrote:
> Add configurations in devicetree for PCIe1, including registers, clocks,
> interrupts and phy setting sequence.
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
> ---
Pretty much identical comments as for patch 4
Konrad
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