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Message-ID: <288be342-952b-4210-afe7-6e194dfd54a9@quicinc.com>
Date: Fri, 15 Nov 2024 12:59:12 +0800
From: Tingwei Zhang <quic_tingweiz@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Dmitry Baryshkov
<dmitry.baryshkov@...aro.org>,
Ziyue Zhang <quic_ziyuzhan@...cinc.com>
CC: <vkoul@...nel.org>, <kishon@...nel.org>, <robh+dt@...nel.org>,
<manivannan.sadhasivam@...aro.org>, <bhelgaas@...gle.com>,
<kw@...ux.com>, <lpieralisi@...nel.org>, <quic_qianyu@...cinc.com>,
<conor+dt@...nel.org>, <neil.armstrong@...aro.org>,
<andersson@...nel.org>, <konradybcio@...nel.org>,
<quic_shashim@...cinc.com>, <quic_kaushalk@...cinc.com>,
<quic_tdas@...cinc.com>, <quic_aiquny@...cinc.com>,
<kernel@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-phy@...ts.infradead.org>
Subject: Re: [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300
On 11/14/2024 9:03 PM, Konrad Dybcio wrote:
> On 14.11.2024 1:10 PM, Dmitry Baryshkov wrote:
>> On Thu, Nov 14, 2024 at 05:54:08PM +0800, Ziyue Zhang wrote:
>>> Add configurations in devicetree for PCIe0, including registers, clocks,
>>> interrupts and phy setting sequence.
>>>
>>> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 +++++-
>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 176 ++++++++++++++++++++++
>>> 2 files changed, 219 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
>>> index 7eed19a694c3..9d7c8555ed38 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
>>> @@ -213,7 +213,7 @@ vreg_l9c: ldo9 {
>>> &gcc {
>>
>> The patch doesn't seem to update the gcc node in qcs8300.dtsi. Is there
>> any reason to have the clocks property in the board data file?
>
> Definitely not. Ziyue, please move that change to the soc dtsi
Gcc node is updated in board device tree due to sleep_clk is defined in
board device tree. Sleep_clk is from PMIC instead SoC so we were
requested to move sleep_clk to board device tree in previous review [1].
[1]https://lore.kernel.org/all/10914199-1e86-4a2e-aec8-2a48cc49ef14@kernel.org/
>
> Konrad
--
Thanks,
Tingwei
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