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Message-ID: <cp2g6j43zlx2njou5qz5tmwsnnzahqtk2hsxkj2ftrzbcmy742@ysca5ica4mvr>
Date: Fri, 15 Nov 2024 08:26:51 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Tingwei Zhang <quic_tingweiz@...cinc.com>
Cc: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Ziyue Zhang <quic_ziyuzhan@...cinc.com>, vkoul@...nel.org, kishon@...nel.org, robh+dt@...nel.org,
manivannan.sadhasivam@...aro.org, bhelgaas@...gle.com, kw@...ux.com, lpieralisi@...nel.org,
quic_qianyu@...cinc.com, conor+dt@...nel.org, neil.armstrong@...aro.org,
andersson@...nel.org, konradybcio@...nel.org, quic_shashim@...cinc.com,
quic_kaushalk@...cinc.com, quic_tdas@...cinc.com, quic_aiquny@...cinc.com,
kernel@...cinc.com, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org
Subject: Re: [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300
On Fri, Nov 15, 2024 at 12:59:12PM +0800, Tingwei Zhang wrote:
> On 11/14/2024 9:03 PM, Konrad Dybcio wrote:
> > On 14.11.2024 1:10 PM, Dmitry Baryshkov wrote:
> > > On Thu, Nov 14, 2024 at 05:54:08PM +0800, Ziyue Zhang wrote:
> > > > Add configurations in devicetree for PCIe0, including registers, clocks,
> > > > interrupts and phy setting sequence.
> > > >
> > > > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
> > > > ---
> > > > arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 +++++-
> > > > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 176 ++++++++++++++++++++++
> > > > 2 files changed, 219 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> > > > index 7eed19a694c3..9d7c8555ed38 100644
> > > > --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> > > > +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
> > > > @@ -213,7 +213,7 @@ vreg_l9c: ldo9 {
> > > > &gcc {
> > >
> > > The patch doesn't seem to update the gcc node in qcs8300.dtsi. Is there
> > > any reason to have the clocks property in the board data file?
> >
> > Definitely not. Ziyue, please move that change to the soc dtsi
>
> Gcc node is updated in board device tree due to sleep_clk is defined in
> board device tree. Sleep_clk is from PMIC instead SoC so we were requested
> to move sleep_clk to board device tree in previous review [1].
Note, the review doesn't talk about sleep_clk at all. The recent
examples (sm8650, x1e80100, sa8775p) still pull the clocks into the SoC
dtsi, but without the freq.
>
> [1]https://lore.kernel.org/all/10914199-1e86-4a2e-aec8-2a48cc49ef14@kernel.org/
> >
> > Konrad
>
>
> --
> Thanks,
> Tingwei
>
> --
> linux-phy mailing list
> linux-phy@...ts.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy
--
With best wishes
Dmitry
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