linux-kernel - Re: [PATCH v3 08/15] cxl/pci: Map CXL PCIe root port and downstream switch port RAS registers

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Message-ID: <33ba3ef6-6dde-4425-9965-73e40d07d4d7@amd.com>
Date: Fri, 15 Nov 2024 13:33:25 -0600
From: "Bowman, Terry" <terry.bowman@....com>
To: Li Ming <ming4.li@...look.com>, linux-cxl@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
 nifan.cxl@...il.com, ming4.li@...el.com, dave@...olabs.net,
 jonathan.cameron@...wei.com, dave.jiang@...el.com,
 alison.schofield@...el.com, vishal.l.verma@...el.com,
 dan.j.williams@...el.com, bhelgaas@...gle.com, mahesh@...ux.ibm.com,
 ira.weiny@...el.com, oohall@...il.com, Benjamin.Cheatham@....com,
 rrichter@....com, nathan.fontenot@....com,
 Smita.KoralahalliChannabasappa@....com, lukas@...ner.de
Subject: Re: [PATCH v3 08/15] cxl/pci: Map CXL PCIe root port and downstream
 switch port RAS registers



On 11/15/2024 9:28 AM, Li Ming wrote:
>
> On 2024/11/14 5:54, Terry Bowman wrote:
>> The CXL mem driver (cxl_mem) currently maps and caches a pointer to RAS
>> registers for the endpoint's root port. The same needs to be done for
>> each of the CXL downstream switch ports and CXL root ports found between
>> the endpoint and CXL host bridge.
>>
>> Introduce cxl_init_ep_ports_aer() to be called for each port in the
>> sub-topology between the endpoint and the CXL host bridge. This function
>> will determine if there are CXL downstream switch ports or CXL root ports
>> associated with this port. The same check will be added in the future for
>> upstream switch ports.
>>
>> Move the RAS register map logic from cxl_dport_map_ras() into
>> cxl_dport_init_ras_reporting(). This eliminates the need for the helper
>> function, cxl_dport_map_ras().
>>
>> cxl_init_ep_ports_aer() calls cxl_dport_init_ras_reporting() to map
>> the RAS registers for CXL downstream switch ports and CXL root ports.
>>
>> cxl_dport_init_ras_reporting() must check for previously mapped registers
>> before mapping. This is necessary because endpoints under a CXL switch
>> may share CXL downstream switch ports or CXL root ports. Ensure the port
>> registers are only mapped once.
>>
>> Signed-off-by: Terry Bowman <terry.bowman@....com>
> [snip]
>
>> +static bool dev_is_cxl_pci(struct device *dev, u32 pcie_type)
>> +{
>> +	struct pci_dev *pdev;
>> +
>> +	if (!dev || !dev_is_pci(dev))
>> +		return false;
>> +
>> +	pdev = to_pci_dev(dev);
>> +
>> +	return (pci_pcie_type(pdev) == pcie_type);
>> +}
>> +
>> +static void cxl_init_ep_ports_aer(struct cxl_ep *ep)
>> +{
>> +	struct cxl_dport *dport = ep->dport;
>> +
>> +	if (dport) {
>> +		struct device *dport_dev = dport->dport_dev;
>> +
>> +		if (dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_DOWNSTREAM) ||
>> +		    dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_ROOT_PORT))
>> +			cxl_dport_init_ras_reporting(dport);
> I think cxl_dport_init_ras_reporting() is needed for both VH case and 
> RCH case. My understanding is that dport_dev could not be a DSP nor a RP 
> in RCH case.
>
> Ming

Good point. I'll look into that. Thanks Ming!

Regards,
Terry