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Message-ID: <20241115165031.GA3344225-robh@kernel.org>
Date: Fri, 15 Nov 2024 10:50:31 -0600
From: Rob Herring <robh@...nel.org>
To: Vikram Sharma <quic_vikramsa@...cinc.com>
Cc: rfoss@...nel.org, todor.too@...il.com, bryan.odonoghue@...aro.org,
mchehab@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
akapatra@...cinc.com, hariramp@...cinc.com, andersson@...nel.org,
konradybcio@...nel.org, hverkuil-cisco@...all.nl,
cros-qcom-dts-watchers@...omium.org, catalin.marinas@....com,
will@...nel.org, linux-arm-kernel@...ts.infradead.org,
linux-media@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
kernel@...cinc.com
Subject: Re: [PATCH v5 1/5] media: dt-bindings: Add qcom,sc7280-camss
On Tue, Nov 12, 2024 at 11:00:28PM +0530, Vikram Sharma wrote:
> Add bindings for qcom,sc7280-camss to support the camera subsystem
> on the SC7280 platform.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@...cinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@...cinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@...cinc.com>
> ---
> .../bindings/media/qcom,sc7280-camss.yaml | 415 ++++++++++++++++++
> 1 file changed, 415 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
> new file mode 100644
> index 000000000000..b27d4af8a64e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
> @@ -0,0 +1,415 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SC7280 CAMSS ISP
> +
> +maintainers:
> + - Azam Sadiq Pasha Kapatrala Syed <akapatra@...cinc.com>
> + - Hariram Purushothaman <hariramp@...cinc.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,sc7280-camss
> +
> + clocks:
> + maxItems: 32
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: gcc_camera_ahb
> + - const: gcc_cam_hf_axi
> + - const: soc_ahb
> + - const: vfe0
> + - const: vfe0_axi
> + - const: vfe0_cphy_rx
> + - const: vfe0_csid
> + - const: vfe0_lite
> + - const: vfe0_lite_cphy_rx
> + - const: vfe0_lite_csid
> + - const: vfe1
> + - const: vfe1_axi
> + - const: vfe1_cphy_rx
> + - const: vfe1_csid
> + - const: vfe1_lite
> + - const: vfe1_lite_cphy_rx
> + - const: vfe1_lite_csid
> + - const: vfe2
> + - const: vfe2_axi
> + - const: vfe2_cphy_rx
> + - const: vfe2_csid
> +
> + interrupts:
> + maxItems: 15
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid0_lite
> + - const: csid1
> + - const: csid1_lite
> + - const: csid2
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: vfe0
> + - const: vfe0_lite
> + - const: vfe1
> + - const: vfe1_lite
> + - const: vfe2
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_0
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + items:
> + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
> + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: ife0
> + - const: ife1
> + - const: ife2
> + - const: top
> +
> + ports:
Nodes go after properties.
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
You have the same description for every port. How does one distinguish
each port?
Looks like there are 5 channels, but I can only guess that looking at
clock and interrupt names...
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + port@4:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + reg:
> + maxItems: 15
> +
> + reg-names:
reg and reg-names go after 'compatible'. See the documented ordering.
> + items:
> + - const: csid0
> + - const: csid0_lite
> + - const: csid1
> + - const: csid1_lite
> + - const: csid2
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: vfe0
> + - const: vfe0_lite
> + - const: vfe1
> + - const: vfe1_lite
> + - const: vfe2
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,camcc-sc7280.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> + #include <dt-bindings/interconnect/qcom,sc7280.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: camss@...f000 {
> + compatible = "qcom,sc7280-camss";
> +
> + reg = <0x0 0x0acb3000 0x0 0x1000>,
> + <0x0 0x0acc8000 0x0 0x1000>,
> + <0x0 0x0acba000 0x0 0x1000>,
> + <0x0 0x0accf000 0x0 0x1000>,
> + <0x0 0x0acc1000 0x0 0x1000>,
> + <0x0 0x0ace0000 0x0 0x2000>,
> + <0x0 0x0ace2000 0x0 0x2000>,
> + <0x0 0x0ace4000 0x0 0x2000>,
> + <0x0 0x0ace6000 0x0 0x2000>,
> + <0x0 0x0ace8000 0x0 0x2000>,
> + <0x0 0x0acaf000 0x0 0x4000>,
> + <0x0 0x0acc4000 0x0 0x4000>,
> + <0x0 0x0acb6000 0x0 0x4000>,
> + <0x0 0x0accb000 0x0 0x4000>,
> + <0x0 0x0acbd000 0x0 0x4000>;
> + reg-names = "csid0",
> + "csid0_lite",
> + "csid1",
> + "csid1_lite",
> + "csid2",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "vfe0",
> + "vfe0_lite",
> + "vfe1",
> + "vfe1_lite",
> + "vfe2";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
> + <&camcc CAM_CC_IFE_2_CLK>,
> + <&camcc CAM_CC_IFE_2_AXI_CLK>,
> + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_2_CSID_CLK>;
> + clock-names = "camnoc_axi",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "gcc_camera_ahb",
> + "gcc_cam_hf_axi",
> + "soc_ahb",
> + "vfe0",
> + "vfe0_axi",
> + "vfe0_cphy_rx",
> + "vfe0_csid",
> + "vfe0_lite",
> + "vfe0_lite_cphy_rx",
> + "vfe0_lite_csid",
> + "vfe1",
> + "vfe1_axi",
> + "vfe1_cphy_rx",
> + "vfe1_csid",
> + "vfe1_lite",
> + "vfe1_lite_cphy_rx",
> + "vfe1_lite_csid",
> + "vfe2",
> + "vfe2_axi",
> + "vfe2_cphy_rx",
> + "vfe2_csid";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid0_lite",
> + "csid1",
> + "csid1_lite",
> + "csid2",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "vfe0",
> + "vfe0_lite",
> + "vfe1",
> + "vfe1_lite",
> + "vfe2";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
> + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "ahb", "hf_0";
> +
> + iommus = <&apps_smmu 0x800 0x4e0>;
> +
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_IFE_1_GDSC>,
> + <&camcc CAM_CC_IFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "ife0", "ife1", "ife2", "top";
> +
> + vdda-phy-supply = <&vreg_l10c_0p88>;
> + vdda-pll-supply = <&vreg_l6b_1p2>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
> --
> 2.25.1
>
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