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Message-Id: <20241120061848.196754-3-keith.zhao@starfivetech.com>
Date: Wed, 20 Nov 2024 14:18:41 +0800
From: keith zhao <keith.zhao@...rfivetech.com>
To: devicetree@...r.kernel.org,
dri-devel@...ts.freedesktop.org
Cc: andrzej.hajda@...el.com,
neil.armstrong@...aro.org,
rfoss@...nel.org,
Laurent.pinchart@...asonboard.com,
jonas@...boo.se,
jernej.skrabec@...il.com,
maarten.lankhorst@...ux.intel.com,
mripard@...nel.org,
tzimmermann@...e.de,
airlied@...il.com,
simona@...ll.ch,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
hjc@...k-chips.com,
heiko@...ech.de,
andy.yan@...k-chips.com,
william.qiu@...rfivetech.com,
xingyu.wu@...rfivetech.com,
kernel@...il.dk,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
p.zabel@...gutronix.de,
changhuang.liang@...rfivetech.com,
keith.zhao@...rfivetech.com,
jack.zhu@...rfivetech.com,
linux-kernel@...r.kernel.org
Subject: [PATCH v5 2/9] riscv: dts: Add display property
Add the display DT nodes in Starfive JH7110 soc-specific DT file.
Signed-off-by: keith zhao <keith.zhao@...rfivetech.com>
---
.../boot/dts/starfive/jh7110-common.dtsi | 125 ++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 41 ++++++
2 files changed, 166 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 9d77713f5361..301b56f2ef0c 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -30,6 +30,25 @@ memory@...00000 {
reg = <0x0 0x40000000 0x1 0x0>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* vout applies for space from this CMA
+ * Without this CMA reservation,
+ * vout may not work properly.
+ */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x20000000>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0x70000000 0x0 0x20000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-restart {
compatible = "gpio-restart";
gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
@@ -62,12 +81,55 @@ codec {
};
};
};
+
+ hdmi_con: hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
};
&cpus {
timebase-frequency = <4000000>;
};
+&dc8200 {
+ status = "okay";
+ crtc_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dc_out0: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dc_out_dpi0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_enc>;
+ };
+
+ };
+
+ dc_out1: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dc_out_dpi1: endpoint@1 {
+ reg = <1>;
+ //remote-endpoint = <&dsi_enc>;
+ };
+
+ };
+ };
+};
+
&dvp_clk {
clock-frequency = <74250000>;
};
@@ -88,6 +150,31 @@ &gmac1_rmii_refin {
clock-frequency = <50000000>;
};
+&hdmi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+ hdmi_enc: endpoint {
+ remote-endpoint = <&dc_out_dpi0>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+};
+
&hdmitx0_pixelclk {
clock-frequency = <297000000>;
};
@@ -366,6 +453,40 @@ &syscrg {
};
&sysgpio {
+ hdmi_pins: hdmi-0 {
+ hdmi-cec-pins {
+ pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
+ GPOEN_SYS_HDMI_CEC_SDA,
+ GPI_SYS_HDMI_CEC_SDA)>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ hdmi-hpd-pins {
+ pinmux = <GPIOMUX(15, GPOUT_HIGH,
+ GPOEN_ENABLE,
+ GPI_SYS_HDMI_HPD)>;
+ input-enable;
+ bias-disable; /* external pull-up */
+ };
+
+ hdmi-scl-pins {
+ pinmux = <GPIOMUX(0, GPOUT_SYS_HDMI_DDC_SCL,
+ GPOEN_SYS_HDMI_DDC_SCL,
+ GPI_SYS_HDMI_DDC_SCL)>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ hdmi-sda-pins {
+ pinmux = <GPIOMUX(1, GPOUT_SYS_HDMI_DDC_SDA,
+ GPOEN_SYS_HDMI_DDC_SDA,
+ GPI_SYS_HDMI_DDC_SDA)>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins: i2c0-0 {
i2c-pins {
pinmux = <GPIOMUX(57, GPOUT_LOW,
@@ -656,3 +777,7 @@ &U74_3 {
&U74_4 {
cpu-supply = <&vdd_cpu>;
};
+
+&voutcrg {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0d8339357bad..d48825822017 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -1203,6 +1203,47 @@ camss: isp@...40000 {
status = "disabled";
};
+ dc8200: lcd-controller@...00000 {
+ compatible = "starfive,jh7110-dc8200";
+ reg = <0x0 0x29400000 0x0 0x100>,
+ <0x0 0x29400800 0x0 0x2000>;
+
+ interrupts = <95>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_AHB>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>,
+ <&hdmitx0_pixelclk>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_PIX>;
+ clock-names = "noc_bus", "dc_core", "axi_core", "ahb",
+ "channel0", "channel1", "hdmi_tx", "dc_parent";
+ resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
+ <&voutcrg JH7110_VOUTRST_DC8200_AHB>,
+ <&voutcrg JH7110_VOUTRST_DC8200_CORE>;
+ reset-names = "axi","ahb", "core";
+
+ starfive,syscon = <&vout_syscon>;
+ };
+
+ hdmi: hdmi@...90000 {
+ compatible = "starfive,jh7110-inno-hdmi";
+ reg = <0x0 0x29590000 0x0 0x4000>;
+ interrupts = <99>;
+
+ clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
+ <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
+ <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>;
+ clock-names = "sysclk", "mclk", "bclk";
+ resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
+ };
+
+ vout_syscon: syscon@...b0000 {
+ compatible = "starfive,jh7110-vout-syscon", "syscon";
+ reg = <0 0x295b0000 0 0x90>;
+ };
+
voutcrg: clock-controller@...c0000 {
compatible = "starfive,jh7110-voutcrg";
reg = <0x0 0x295c0000 0x0 0x10000>;
--
2.34.1
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