linux-kernel - Re: [PATCH 0/8] Add GCE support for MT8196

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Message-ID: <778f7f7c01d395e911ae32f168c17d1f6d95ea40.camel@mediatek.com>
Date: Thu, 21 Nov 2024 11:21:35 +0000
From: Jason-JH Lin (林睿祥) <Jason-JH.Lin@...iatek.com>
To: "chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>, "mchehab@...nel.org"
	<mchehab@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
	"robh@...nel.org" <robh@...nel.org>, "matthias.bgg@...il.com"
	<matthias.bgg@...il.com>, "jassisinghbrar@...il.com"
	<jassisinghbrar@...il.com>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	Singo Chang (張興國) <Singo.Chang@...iatek.com>,
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	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, "simona@...ll.ch"
	<simona@...ll.ch>, Moudy Ho (何宗原)
	<Moudy.Ho@...iatek.com>, Nancy Lin (林欣螢)
	<Nancy.Lin@...iatek.com>, "dri-devel@...ts.freedesktop.org"
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	<Project_Global_Chrome_Upstream_Group@...iatek.com>, "airlied@...il.com"
	<airlied@...il.com>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 0/8] Add GCE support for MT8196

Hi Angelo,

On Thu, 2024-11-21 at 09:55 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 21/11/24 05:25, Jason-JH.Lin ha scritto:
> > This patch series adds support for the MediaTek MT8196 SoC in the
> > CMDQ
> > driver and related subsystems. The changes include adding
> > compatible
> > names and properties, updating driver data to accommodate hardware
> > changes, and modifying the CMDQ API to support non-subsys ID
> > hardware.
> > 
> > Jason-JH.Lin (8):
> >    dt-bindings: mailbox: mediatek: Add GCE header file for MT8196
> >    dt-bindings: mailbox: mediatek: Add MT8196 support for gce-
> > mailbox
> >    mailbox: mtk-cmdq: Add driver data to support for MT8196
> >    soc: mediatek: mtk-cmdq: Add unsupported subsys ID programing
> > flow
> >    soc: mediatek: mtk-cmdq: Add mminfra_offset compatibility for
> > DRAM
> >      address
> >    soc: mediatek: Add pa_base due to CMDQ API change
> >    drm/mediatek: Add pa_base due to CMDQ API change
> >    media: mediatek: mdp3: Add pa_base due to CMDQ API change
> > 
> >   .../mailbox/mediatek,gce-mailbox.yaml         |    4 +
> >   drivers/gpu/drm/mediatek/mtk_ddp_comp.c       |    6 +-
> >   drivers/mailbox/mtk-cmdq-mailbox.c            |  107 +-
> >   .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c    |    4 +-
> >   .../platform/mediatek/mdp3/mtk-mdp3-comp.h    |    4 +-
> >   drivers/soc/mediatek/mtk-cmdq-helper.c        |  133 +-
> >   drivers/soc/mediatek/mtk-mmsys.c              |    1 +
> >   drivers/soc/mediatek/mtk-mutex.c              |    2 +-
> >   .../dt-bindings/mailbox/mediatek,mt8196-gce.h | 1449
> > +++++++++++++++++
> >   include/linux/mailbox/mtk-cmdq-mailbox.h      |    3 +
> >   include/linux/soc/mediatek/mtk-cmdq.h         |   22 +-
> >   11 files changed, 1698 insertions(+), 37 deletions(-)
> >   create mode 100755 include/dt-bindings/mailbox/mediatek,mt8196-
> > gce.h
> > 
> 
> 
> Hello Jason,
> I had a fast look at the changes that you're proposing with this
> series.
> 
> The reasons behind this are more or less understood on my side, but
> the
> actual changes look a bit odd in the sense that passing a physical
> address
> like this, on a first glance, not only looks like it may be
> dangerous, but
> also looks like there's a lot of room for improvement.
> 

It's because hardware subsys ID for GCE is no longer to be used in
MT8196. So we need to put the PA into the instruction then GCE can know
where to write the configuration.

> Can you please point me at some driver/code (or a reference downsream
> kernel
> for this SoC, which would be even better) so that I can take a look
> at how
> is that being used?

Before MT8196, the most general use case is in the mtk_ddp_write(),
mtk_ddp_write_mask() at mtk_ddp_comp.c.
The client drivers will pass the `struct cmdq_client_reg` which has
stored the subsys ID, offset ans size parsing from the DTS node.

The client drivers use the subsys ID via CMDQ API to generate the
instructions. And GCE knows where the subsys ID is mapping to the
corresponding hardware register pa_base, so it can configure the
hardware register correctly.

That's the main change in this series and feel free to ask me more
details. Or if you have anything want to know rapidly.
You can find me in the Google Chat :-)

Regards,
Jason-JH.Lin

> 
> Thanks,
> Angelo